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US 12,597,934 B2Granted
Clock data recovery circuit and apparatus including the same
AssigneesSamsung Electronics Co., Ltd., Seoul National University R&Db Foundation
InventorsWooseok Choi, Jihee Kim
Life of this patent
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Abstract
A clock data recovery circuit including: a sampler to sample a comparison result between an input data signal and multiple reference voltages or to sample the input data signal based on a recovered clock signal; and a control circuit to output a control signal for controlling a phase of the recovered clock signal based on a K signal, an up signal, and a down signal.
Claims20
A clock data recovery circuit comprising:
- a sampler configured to sample a comparison result between an input data signal and multiple reference voltages or to sample the input data signal based on a recovered clock signal;
- and
- a control circuit configured to output a control signal for controlling a phase of the recovered clock signal based on a K signal, an up signal, and a down signal,
- wherein the sampler comprises:
- a first sampler configured to output a data sample signal by sampling the input data signal at an edge of the recovered clock signal;
- a second sampler configured to output an error signal by comparing a voltage level of the input data signal with a first reference voltage at the edge of the recovered clock signal;
- and
- a third sampler configured to output an eye monitoring signal by comparing the voltage level of the input data signal with a second reference voltage at the edge of the recovered clock signal or an edge of a delayed recovered clock signal, and
- the control circuit comprises:
- a phase detector configured to output the up signal or the down signal based on the data sample signal and the error signal;
- a first logic configured to output the K signal based on the data sample signal and the eye monitoring signal;
- a second logic configured to output a phase error signal based on the K signal, the up signal, and the down signal;
- and
- a phase interpolator (PI) code generator configured to output the control signal based on the phase error signal.
11 more elements
An apparatus comprising:
- a reception circuit;
- and
- a transmission circuit configured to transmit an input data signal to the reception circuit through a channel,
- wherein the reception circuit comprises:
- a sampler configured to sample a comparison result between the input data signal and multiple reference voltages or to sample the input data signal based on a recovered clock signal;
- and
- a control circuit configured to output a control signal for controlling a phase of the recovered clock signal based on a K signal, an up signal, and a down signal,
- wherein the sampler comprises:
- a first sampler configured to output a data sample signal by sampling the input data signal at an edge of the recovered clock signal;
- a second sampler configured to output an error signal by comparing a voltage level of the input data signal with a first reference voltage at the edge of the recovered clock signal;
- and
- a third sampler configured to output an eye monitoring signal by comparing the voltage level of the input data signal with a second reference voltage at the edge of the recovered clock signal or an edge of a delayed recovered clock signal, and
- the control circuit comprises:
- a phase detector configured to output the up signal or the down signal based on the data sample signal and the error signal;
- a first logic configured to output the K signal based on the data sample signal and the eye monitoring signal;
- a second logic configured to output a phase error signal based on the K signal, the up signal, and the down signal;
- and
- a phase interpolator (PI) code generator configured to output the control signal based on the phase error signal.
15 more elements
A phase detector comprising:
- a phase detection circuit configured to output an up signal or a down signal based on a data sample signal and an error signal;
- a first circuit configured to output a K signal based on the data sample signal and an eye monitoring signal;
- and
- a second circuit configured to output a phase error signal based on the K signal, the up signal, and the down signal.
1 more element
Dependencies are inferred from the claim text.