US 12,597,931 B2 · Clock insertion delay systems and methods

Abstract

Various techniques are provided to efficiently synchronize clock and data signals in programmable logic devices (PLDs). In one example, a method comprises configuring an intellectual property (IP) block of the PLD to receive a first clock signal and a first data signal at a first component of the IP block, determining a delay associated with the first clock signal between a first input and the first component, configuring a programmable logic cell (PLC) to receive a second clock signal and output the first data signal to the IP block, determining a delay period to synchronize the first clock signal and the first data signal at the first component of the IP block, and configuring an adjustable delay element to apply the delay period to the second clock signal to synchronize the first clock signal and the first data signal at the first component of the IP block.

Claims20

Dependent claims

A method for synchronizing data signals and clock signals in a programmable logic device (PLD), the method comprising:

configuring an intellectual property (IP) block of the PLD to receive a first clock signal and a first data signal at a first component of the IP block;
determining a delay associated with the first clock signal between a first input and the first component;
configuring a plurality of programmable logic cells (PLCs) to receive a second clock signal;
configuring a particular one of the PLCs to output the first data signal to the IP block;
determining a delay period to synchronize the first clock signal and the first data signal at the first component of the IP block, wherein the delay period is determined based on the delay associated with the first clock signal between the first input and the first component;
and
configuring an adjustable delay element to apply the delay period to the second clock signal to synchronize the first clock signal and the first data signal at the first component of the IP block by adjusting the second clock signal to delay output of the first data signal by the delay period.

4 more elements

Dependencies are inferred from the claim text.

Clock insertion delay systems and methods

Life of this patent

Clock insertion delay systems and methods

Life of this patent

Abstract

Claims20