Deterioration inhibiting circuit

A deterioration inhibiting circuit comprising:

• a switchover circuit configured to inhibit characteristic deterioration of a pair of MOS transistors included in a differential pair circuit, wherein:
• the differential pair circuit has a first input terminal and a second input terminal, and is configured to output an output signal according to a difference between a pair of input signals provided to the first input terminal and the second input terminal;
• the pair of MOS transistors are
• a first transistor whose gate is connected to the first input terminal, and
• a second transistor whose gate is connected to the second input terminal;
• the switchover circuit is further configured to execute switchover between a first state and a second state;
• in the first state, the switchover circuit applies a first voltage to the gate of the first transistor and applies a second voltage to the gate of the second transistor, and in the second state, the switchover circuit applies the second voltage to the gate of the first transistor and applies the first voltage to the gate of the second transistor;
• and
• the first voltage is higher than an intermediate voltage that is a half of a power supply, by a predetermined threshold voltage, and the second voltage is lower than the intermediate voltage by the predetermined threshold voltage.