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US 12,597,914 B2Granted
Oscillating signal generating circuit and a semiconductor apparatus using the same
AssigneeSK hynix Inc.
InventorsSun Ki Cho, Yang Ho Sur, Ic Su Oh
Life of this patent
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Abstract
An oscillating signal generating circuit drives an oscillating signal to a first logic level based on a first control signal, which is generated by delaying the oscillating signal through a clock delaying circuit, and drives the oscillating signal to a second logic level based on a second control signal, which is generated by delaying the oscillating signal by a fixed delay amount.
Claims16
An oscillating signal generating circuit comprising:
- a first clock delaying circuit configured to delay an oscillating signal;
- a set pulse generator configured to generate a set pulse signal based on an output from the first clock delaying circuit;
- a reset pulse generator configured to receive the set pulse signal and configured to generate a reset pulse signal;
- and
- an oscillating driver configured to drive the oscillating signal to a first logic level based on the set pulse signal and configured to drive the oscillating signal to a second logic level based on the reset pulse signal.
2 more elements
An oscillating signal generating circuit comprising:
- a first clock delaying circuit configured to delay an oscillating signal;
- a second clock delaying circuit configured to delay the oscillating signal;
- a selecting circuit configured to output one of an output signal from the first clock delaying circuit and an output signal from the second clock delaying circuit based on a selection signal;
- a set pulse generator configured to generate a set pulse signal based on the output signal from the selecting circuit;
- a reset pulse generator configured to generate a reset pulse signal based on the set pulse signal;
- and
- an oscillating driver configured to generate the oscillating signal based on the set pulse signal and the reset pulse signal.
4 more elements
An oscillating signal generating circuit comprising:
- a first clock delaying circuit configured to delay an oscillating signal;
- a second clock delaying circuit configured to delay the oscillating signal;
- a third clock delaying circuit configured to delay the oscillating signal;
- a fourth clock delaying circuit configured to delay the oscillating signal;
- a selecting circuit configured to output one of output signals from the first to fourth clock delaying circuit based on a selection signal;
- a set pulse generator configured to generate a set pulse signal based on the output signal from the selecting circuit;
- a reset pulse generator configured to generate a reset pulse signal based on the set pulse signal;
- and
- an oscillating driver configured to generate the oscillating signal based on the set pulse signal and the reset pulse signal.
6 more elements
Dependencies are inferred from the claim text.