Superconducting data input system

A method for generating superconducting data, the method comprising:

• providing a clock signal to a pulse generator and to a superconducting data input system;
• providing a current pulse from the pulse generator to the superconducting data input system or not providing the current pulse from the pulse generator to the superconducting data input system at each of a first phase of the clock signal and a second phase of the clock signal;
• providing a first superconducting data signal from the superconducting data input system at the first phase of the clock signal, the first superconducting data signal having a first data state in response to the current pulse being provided at the first phase of the clock signal and having a second data state in response to the current pulse not being provided at the first phase of the clock signal;
• and
• providing a second superconducting data signal from the superconducting data input system at the second phase of the clock signal that is opposite the first phase of the clock signal, the second superconducting data signal having the first data state in response to the current pulse being provided at the second phase of the clock signal and having the second data state in response to the current pulse not being provided at the second phase of the clock signal.

A superconducting circuit system comprising:

• a pulse generator that generates a current pulse or does not generate the current pulse at each of a first phase of the clock signal and a second phase of the clock signal that is opposite the first phase;
• a superconducting circuit;
• and
• a superconducting data input system comprising:
• an inductive coupler that generates a first bias current and a second bias current in response to receiving the current pulse;
• a first clocked receiver configured to provide a first superconducting data signal to the superconducting circuit, the first superconducting data signal having a first data state in response to the first bias current at the first phase of the clock signal and having a second data state in response to not receiving the first bias current at the first phase of the clock signal;
• and
• a second clocked receiver configured to provide a second superconducting data signal to the superconducting circuit, the second superconducting data signal having the first data state in response to the second bias current at the second phase of the clock signal, and having the second data state in response to not receiving the second bias current at the second phase of the clock signal.