# US 12,597,857 B2 · Adaptive charge pump voltage supply frequency switch > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,597,857 B2 - Document ID: US12597857B2 - Status: Granted - Kind: B2 - Application number: 18/664,665 - Filed: 2024-05-15 - Published: 2024-11-28 - Granted: 2026-04-07 - Earliest claimed: 2023-05-25 - Assignees: pSemi Corporation - Applicants: pSemi Corporation - Inventors: Gary Chunshien Wu; Gregory Szczeszynski - Web page: https://patentgrep.com/patent/US12597857B2 ## CPC - H02M 3/07: using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} - H03K 3/0315: {Ring oscillators} - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Circuits and methods that enable a charge pump to provide sufficient charge to the gate of a switch NFET to turn the NFET ON within a specified switching time requirement but with minimal generation of electronic noise. An embodiment includes a dual-oscillator circuit configured to output from a first oscillator a first frequency signal from a first oscillator during normal operation, and to output from a second oscillator a second frequency signal higher in frequency than the first frequency signal for a selected time determined by a counter. An embodiment includes a charge pump coupled to the dual-oscillator circuit and configured to output an electrical charge as a function of an applied frequency signal from the dual-oscillator circuit, wherein application of the second frequency signal output during counting increases the amount of electrical charge output by the charge pump. ## Claims ### Claim 1 A dual-oscillator circuit, comprising: an output circuit configured to provide an output; a first oscillator configured to provide a first frequency signal having a first frequency to the output circuit; a second oscillator configured to provide a second frequency signal having a second frequency to the output circuit, wherein the second frequency is greater than the first frequency; and a counter coupled to the output circuit and configured to generate one or more enable signals having a state enabling the output circuit to provide either the first frequency signal or the second frequency signal as the output. ### Claim 2 (depends on 1) The dual-oscillator circuit of claim 1, wherein the counter is configured to commence counting in response to a control signal applied to the counter, and wherein the counter is configured to generate enable signals that enable the output circuit to provide the second frequency signal as the output if counting. ### Claim 3 (depends on 1) The dual-oscillator circuit of claim 1, wherein the counter is configured to commence counting in response to either a first control signal or a second control signal applied to the counter, and wherein the counter is configured to generate enable signals that enable the output circuit to provide the second frequency signal as the output if counting. ### Claim 4 (depends on 1) A system, comprising: the dual-oscillator circuit of claim 1; and a charge pump having an output node, and configured to output an electrical charge at the output node of the charge pump, wherein the electrical charge is based on the output of the output circuit, wherein the electrical charge is greater if the output of the output circuit is the second frequency signal than if the output of the output circuit is the first frequency signal, wherein the counter is configured to change a count value from an initial value to a final value according to a received clock signal, and wherein the counter is configured to generate enable signals that enable the output circuit to provide the second frequency signal as the output of the output circuit if changing the count value. ### Claim 5 (depends on 4) The dual-oscillator circuit of claim 4, further including a switch having at least one through-path comprising a pair of NFETs having conduction channels coupled in series, each NFET including a gate coupled to the output node of the charge pump, each through-path coupling a corresponding input terminal to an output terminal. ### Claim 6 (depends on 1) The dual-oscillator circuit of claim 1, wherein the counter is configured to conditionally change a count value from an initial value in response to a received clock signal, and is configured to generate the one or more enable signals based on whether the count value is being changed. ### Claim 7 (depends on 1) The dual-oscillator circuit of claim 1, wherein the counter is configured to enable the second oscillator for a specified number of clock cycles of the second oscillator. ### Claim 8 A dual-oscillator circuit including: a first oscillator having an enable input and an output configured to output a first frequency signal; a second oscillator having an enable input and an output configured to output a second frequency signal higher in frequency than the first frequency signal; a multiplexor having a first input coupled to the output of the first oscillator, a second input coupled to the output of the second oscillator, a selector input, and an output; and a counter, including: a clock input coupled to the output of the second oscillator; a count-enable input; a first output coupled to the enable input of the first oscillator; a second output coupled to the enable input of the second oscillator and to the selector input of the multiplexor; wherein the counter is configured to assert a first enable signal on the first output and de-assert a second enable signal on the second output if not counting to couple the first frequency signal to the output of the multiplexor, and to assert the second enable signal on the second output if counting to couple the second frequency signal to the output of the multiplexor. ### Claim 9 (depends on 8) The dual-oscillator circuit of claim 8, wherein the counter is configured to commence counting in response to a control signal applied to the count-enable input. ### Claim 10 (depends on 8) The dual-oscillator circuit of claim 8, wherein the counter is configured to commence counting in response to either a first control signal applied to the count-enable input or a second control signal applied to the count-enable input. ### Claim 11 (depends on 6) A system, comprising: the dual-oscillator circuit of claim 6; and a charge pump having an output node, and configured to output an electrical charge at the output node of the charge pump, wherein the electrical charge is based on the signal coupled to the output of the multiplexor, wherein the electrical charge is greater if the output of the multiplexor is coupled to the second frequency signal than if the output of the multiplexor is coupled to the first frequency signal, wherein the counter is configured to change a count value from an initial value to a final value according to a received clock signal, and wherein the counter is configured to generate enable signals that enable the multiplexor to couple the second frequency signal to the output of the multiplexor if changing the count value. ### Claim 12 (depends on 11) The dual-oscillator circuit of claim 11, further including a switch having at least one through-path comprising a pair of NFETs having conduction channels coupled in series, each NFET including a gate coupled to the output node of the charge pump, each through-path coupling a corresponding input terminal to an output terminal. ### Claim 13 (depends on 12) The dual-oscillator circuit of claim 12, wherein the counter is configured to commence counting in response to a control signal applied to the count-enable input, the control signal indicating selection of a corresponding through-path and indicating application of a control voltage to the gates of the pair of NFETs. ### Claim 14 (depends on 12) The dual-oscillator circuit of claim 12, wherein the counter is configured to commence counting in response to either a first control signal applied to the count-enable input or a second control signal applied to the count-enable input, the first control signal and the second control signal each indicating selection of a corresponding through-path and indicating application of a control voltage to the gates of the pair of NFETs of the corresponding through-path. ### Claim 15 (depends on 8) The dual-oscillator circuit of claim 8, further including a low-pulse extender circuit coupled between the second output of the counter and the enable input of the second oscillator. ### Claim 16 (depends on 8) The dual-oscillator circuit of claim 8, wherein the counter is a down-counter. ### Claim 17 (depends on 8) The dual-oscillator circuit of claim 8, wherein the counter includes a count select input configured to receive an n-bit count value, where n≥1, that determines a duration of the counting of the counter. ### Claim 18 An electronic switch circuit including: a first oscillator having an enable input and an output configured to output a first frequency signal; a second oscillator having an enable input and an output configured to output a second frequency signal higher in frequency than the first frequency signal; a multiplexor having a first input coupled to the output of the first oscillator, a second input coupled to the output of the second oscillator, a selector input, and an output; a counter, including: a clock input coupled to the output of the second oscillator; a count-enable input; a first output coupled to the enable input of the first oscillator; a second output coupled to the enable input of the second oscillator and to the selector input of the multiplexor; a charge pump coupled to the multiplexor output, the charge pump having an output node, and configured to output an electrical charge at the output node of the charge pump, wherein the electrical charge is based on the signal coupled to the output of the multiplexor, wherein the electrical charge is greater if the output of the multiplexor is coupled to the second frequency signal than if the output of the multiplexor is coupled to the first frequency signal, a switch having at least one through-path comprising a pair of NFETs having conduction channels coupled in series, each NFET including a gate coupled to the output of the charge pump, each through-path coupling a corresponding input terminal to an output terminal; wherein the counter is configured to assert a first enable signal on the first output and de-assert a second enable signal on the second output if not counting to couple the first frequency signal to the output of the multiplexor, and to assert a control the second enable signal on the second output if counting to couple the second frequency signal to the output of the multiplexor; and wherein the counter is configured to commence counting in response to a control signal applied to the count-enable input, the control signal indicating selection of a corresponding through-path and indicating application of a control voltage to the gates of the pair of NFETs of the corresponding through-path. ### Claim 19 (depends on 18) The electronic switch circuit of claim 18, wherein the counter is configured to commence counting in response to either a first control signal applied to the count-enable input or a second control signal applied to the count-enable input, the first control signal and the second control signal each indicating selection of a corresponding through-path and indicating application of a control voltage to the gates of the pair of NFETs of the corresponding through-path. ### Claim 20 (depends on 18) The electronic switch circuit of claim 18, further including a low-pulse extender circuit coupled between the second output of the counter and the enable input of the second oscillator. ### Claim 21 (depends on 18) The electronic switch circuit of claim 18, wherein the counter is a down-counter. ### Claim 22 (depends on 18) The electronic switch circuit of claim 18, wherein the counter includes a count select input configured to receive an n-bit count value, where n≥1, that determines a duration of counting by the counter.