# US 12,597,769 B2 · Electrostatic discharge protection device

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- Number: US 12,597,769 B2
- Document ID: US12597769B2
- Status: Granted
- Kind: B2
- Application number: 18/296,541
- Filed: 2023-04-06
- Published: 2024-07-04
- Granted: 2026-04-07
- Earliest claimed: 2023-01-04
- Assignees: VIA Technologies, Inc.
- Applicants: Via Technologies, Inc.
- Inventors: Ke-Yuan Chen; Tzu-Chun Liu
- Web page: https://patentgrep.com/patent/US12597769B2

## CPC

- H02H 9/005: {avoiding undesired transient conditions}
- H10D 89/713: {including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices}
- H02H 9/04: responsive to excess voltage (lightning arrestors H01C7/12, H01C8/04, H01G9/18, H01T)
- H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An electrostatic discharge protection device is provided. The electrostatic discharge protection device includes first and second N-type and P-type and third P-type doped regions in the first and second N-type well regions in a P-type semiconductor substrate. First and second P-type well regions are in the first N-type well region. Third N-type, fourth P-type and N-type and fifth P-type doped regions are in the first and second P-type well regions. Fifth N-type and sixth P-type doped regions are in the third P-type well region in the second N-type well region. The first and second N-type doped regions are directly electrically connected to the fifth and sixth P-type doped regions, respectively. The first P-type and fifth N-type, the second P-type and third N-type, and the third P-type doped region and the fourth N-type and P-type doped regions are electrically connected to input/output, power supply and ground terminals.

## Claims

### Claim 1

An electrostatic discharge protection device, comprising:
a P-type semiconductor substrate;
a first N-type well region located in the P-type semiconductor substrate;
a first N-type doped region located in the first N-type well region;
a first P-type doped region located in the first N-type well region, wherein the first P-type doped region and the first N-type doped region are arranged side-by-side and spaced apart from each other;
a second N-type well region located in the P-type semiconductor substrate, wherein the first N-type well region and the second N-type well region are arranged side-by-side and spaced apart from each other;
a second N-type doped region located in the second N-type well region;
a second P-type doped region located in and in contact with the second N-type well region;
a third P-type doped region located in and in contact with the second N-type well region, wherein the second N-type doped region, the second P-type doped region and the third P-type doped region are arranged side-by-side and spaced apart from one another;
a first P-type well region located in the first N-type well region;
a third N-type doped region located in the first P-type well region;
a fourth P-type doped region located in the first P-type well region, wherein the third N-type doped region and the fourth P-type doped region are arranged side-by-side and spaced apart from each other;
a second P-type well region located in the first N-type well region, wherein the first P-type well region and the second P-type well region are arranged side-by-side and spaced apart from each other, and the first P-type well region and the second P-type well region are surrounded by the first N-type well region;
a fourth N-type doped region located in the second P-type well region;
a fifth P-type doped region located in the second P-type well region, wherein the fourth N-type doped region and the fifth P-type doped region are arranged side-by-side and spaced apart from each other;
a third P-type well region located in the second N-type well region;
a fifth N-type doped region located in the third P-type well region; and
a sixth P-type doped region located in the third P-type well region, wherein the fifth N-type doped region and the sixth P-type doped region are arranged side-by-side and spaced apart from each other;
wherein the first N-type doped region is directly electrically connected to the fifth P-type doped region,
wherein the second N-type doped region is directly electrically connected to the sixth P-type doped region,
wherein the first P-type doped region and the fifth N-type doped region are electrically connected to an input/output terminal,
wherein the second P-type doped region and the third N-type doped region are electrically connected to a power supply terminal, and
wherein the third P-type doped region, the fourth N-type doped region and the fourth P-type doped region are electrically connected to a ground terminal.

### Claim 2 (depends on 1)

The electrostatic discharge protection device as claimed in claim 1, wherein the first N-type well region and the second N-type well region are arranged side-by-side along a first direction and spaced apart from each other.

### Claim 3 (depends on 2)

The electrostatic discharge protection device as claimed in claim 2, wherein the first P-type well region is located between the first N-type doped region and the first P-type doped region along the first direction.

### Claim 4 (depends on 2)

The electrostatic discharge protection device as claimed in claim 2, wherein the first P-type well region and the second P-type well region are respectively located on opposite sides of the first P-type doped region substantially parallel to a second direction, and wherein the first P-type well region and the second P-type well region are spaced apart from the first P-type doped region along the first direction.

### Claim 5 (depends on 2)

The electrostatic discharge protection device as claimed in claim 2, wherein the second P-type doped region and the third P-type doped region are respectively located on opposite sides of the third P-type well region substantially parallel to a second direction, and wherein the second P-type doped region and the third P-type doped region are spaced apart from the third P-type well region along the first direction.

### Claim 6 (depends on 1)

The electrostatic discharge protection device as claimed in claim 1, wherein in a cross-sectional view, the first N-type well region and the second N-type well region have a first depth, the first P-type well region, the second P-type well region and the third P-type well region have a second depth, and wherein the first depth is greater than the second depth.

### Claim 7 (depends on 1)

The electrostatic discharge protection device as claimed in claim 1, further comprising:
a first N-type deep well region located below the first N-type well region, the first P-type well region and the second P-type well region, wherein the first N-type deep well region is in contact with bottom surfaces of the first N-type well region, the first P-type well region and the second P-type well region.

### Claim 8 (depends on 7)

The electrostatic discharge protection device as claimed in claim 7, wherein in a cross-sectional view, a boundary of the first N-type deep well region is aligned with a boundary of the first N-type well region.

### Claim 9 (depends on 7)

The electrostatic discharge protection device as claimed in claim 7, further comprising:
a second N-type deep well region located below the first N-type well region and the third P-type well region and spaced apart from the first N-type deep well region, wherein the second N-type deep well region is in contact with bottom surfaces of the first N-type well region and the third P-type well region.

### Claim 10 (depends on 9)

The electrostatic discharge protection device as claimed in claim 9, wherein in a cross-sectional view, a boundary of the second N-type deep well region is aligned with a boundary of the second N-type well region.

### Claim 11 (depends on 9)

The electrostatic discharge protection device as claimed in claim 9, wherein in a cross-sectional view, the first N-type well region and the second N-type well region have a first depth, the first P-type well region, the second P-type well region and the third P-type well region have a second depth, and wherein the first depth is equal to the second depth.

### Claim 12 (depends on 11)

The electrostatic discharge protection device as claimed in claim 11, wherein in the cross-sectional view, the first N-type deep well region and the second N-type deep well region have a third depth, and wherein the third depth is greater than the first depth and the second depth.

### Claim 13 (depends on 1)

The electrostatic discharge protection device as claimed in claim 1, wherein:
the first P-type doped region and the first N-type well region form a first parasitic diode,
the fifth P-type doped region, the second P-type well region and the fourth N-type doped region form a second parasitic diode, wherein the first parasitic diode and the second parasitic diode are connected in series,
the first P-type doped region, the first N-type well region and the second P-type well region form a first parasitic bipolar junction transistor,
the fourth N-type doped region, the second P-type well region and the first N-type well region form a second parasitic bipolar junction transistor,
a base of the first parasitic bipolar junction transistor is electrically connected to a collector of the second parasitic bipolar junction transistor, and a base of the second parasitic bipolar junction transistor is electrically connected to a collector of the first parasitic bipolar junction transistor to form a first parasitic semiconductor controlled rectifier,
the base of the first parasitic bipolar junction transistor is electrically connected to a cathode of the first parasitic diode, and
the base of the second parasitic bipolar junction transistor is electrically connected to an anode of the second parasitic diode.

### Claim 14 (depends on 13)

The electrostatic discharge protection device as claimed in claim 13, wherein when an electrostatic discharge event occurs between the input/output terminal and the ground terminal, the first parasitic diode and the second parasitic diode are triggered to ON, and the first parasitic bipolar junction transistor and the second parasitic bipolar junction transistor are triggered to ON, and the first parasitic semiconductor controlled rectifier is accordingly triggered to ON.

### Claim 15 (depends on 1)

The electrostatic discharge protection device as claimed in claim 1, wherein:
the first P-type doped region and the first N-type well region form a first parasitic diode,
the second P-type well region, the fifth P-type doped region and the fourth N-type doped region form a second parasitic diode, wherein the first parasitic diode and the second parasitic diode are connected in series,
the third N-type doped region, the first P-type well region and the first N-type well region form a third parasitic bipolar junction transistor,
the first P-type doped region, the first N-type well region and the first P-type well region form a fourth parasitic bipolar junction transistor,
a base of the third parasitic bipolar junction transistor is electrically connected to a collector of the fourth parasitic bipolar junction transistor, and a base of the fourth parasitic bipolar junction transistor is electrically connected to a collector of third parasitic bipolar junction transistor to form a second parasitic semiconductor controlled rectifier, and
the base of the fourth parasitic bipolar junction transistor is electrically connected to a cathode of the first parasitic diode, and is electrically connected to an anode of the second parasitic diode through a conductive line.

### Claim 16 (depends on 15)

The electrostatic discharge protection device as claimed in claim 15, wherein when an electrostatic discharge event occurs between the input/output terminal and the power supply terminal, the first parasitic diode and the second parasitic diode are triggered to ON, and the third parasitic bipolar junction transistor and the fourth parasitic bipolar junction transistor are triggered to ON, and the second parasitic semiconductor controlled rectifier is accordingly triggered to ON.

### Claim 17 (depends on 1)

The electrostatic discharge protection device as claimed in claim 1, wherein:
the second P-type doped region and the second N-type well region form a fourth parasitic diode,
the sixth P-type doped region, the third P-type well region and the fifth N-type doped region form a fifth parasitic diode, wherein the fourth parasitic diode and the fifth parasitic diode are connected in series,
the second P-type doped region, the second N-type well region and the third P-type well region form a fifth parasitic bipolar junction transistor,
the fifth N-type doped region, the third P-type well region and the second N-type well region form a sixth parasitic bipolar junction transistor,
a base of the fifth parasitic bipolar junction transistor is electrically connected to a collector of the sixth parasitic bipolar junction transistor, and a base of the sixth parasitic bipolar junction transistor is electrically connected to a collector of the fifth parasitic bipolar junction transistor to form a third parasitic semiconductor controlled rectifier,
the base of the fifth parasitic bipolar junction transistor is electrically connected to a cathode of the fourth parasitic diode, and
the base of the sixth parasitic bipolar junction transistor is electrically connected to an anode of the fifth parasitic diode.

### Claim 18 (depends on 17)

The electrostatic discharge protection device as claimed in claim 17, wherein when an electrostatic discharge event occurs between the power supply terminal and the input/output terminal, the fourth parasitic diode and the fifth parasitic diode are triggered to ON, and the fifth parasitic bipolar junction transistor and the sixth parasitic bipolar junction transistor are triggered to ON, and the third parasitic semiconductor controlled rectifier is accordingly triggered to ON.

### Claim 19 (depends on 1)

The electrostatic discharge protection device as claimed in claim 1, wherein:
the sixth P-type doped region, the third P-type well region and the fifth N-type doped region form a fifth parasitic diode,
the third P-type doped region and the second N-type well region form a sixth parasitic diode, wherein the fifth parasitic diode and the sixth parasitic diode are connected in series,
the fifth N-type doped region, the third P-type well region and the second N-type well region form a sixth parasitic bipolar junction transistor,
the third P-type doped region, the second N-type well region and the third P-type well region form a seventh parasitic bipolar junction transistor,
a base of the sixth parasitic bipolar junction transistor is electrically connected to a collector of the seventh parasitic bipolar junction transistor, and a base of the seventh parasitic bipolar junction transistor is electrically connected a collector of sixth parasitic bipolar junction transistor to form a fourth parasitic semiconductor controlled rectifier,
the base of the seventh parasitic bipolar junction transistor is electrically connected to a cathode of the sixth parasitic diode, and
the base of the sixth parasitic bipolar junction transistor is electrically connected to an anode of the fifth parasitic diode.

### Claim 20 (depends on 19)

The electrostatic discharge protection device as claimed in claim 19, wherein when an electrostatic discharge event occurs between the ground terminal and the input/output terminal, the fifth parasitic diode and the sixth parasitic diode are triggered to ON, and the sixth parasitic bipolar junction transistor and the seventh parasitic bipolar junction transistor are triggered to ON, and the fourth parasitic semiconductor controlled rectifier is accordingly triggered to ON.