# US 12,597,764 B2 · Safety test circuit and method

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- Number: US 12,597,764 B2
- Document ID: US12597764B2
- Status: Granted
- Kind: B2
- Application number: 18/545,498
- Filed: 2023-12-19
- Published: 2025-06-19
- Granted: 2026-04-07
- Earliest claimed: 2023-12-19
- Assignees: Rockwell Automation Technologies, Inc.
- Applicants: Rockwell Automation Technologies, Inc.
- Inventors: Wojciech Maciej Jurczak; Daniel Marcin Strzelecki
- Web page: https://patentgrep.com/patent/US12597764B2

## CPC

- H02H 1/0007: {concerning the detecting means (in general G01R or other subclasses of G01; reed switches H01H71/2445)}
- H02H 3/044: {Checking correct functioning of protective arrangements, e.g. by simulating a fault (for differential current circuit breakers H02H3/335)}
- G01R 31/3277: {of low voltage devices, e.g. domestic or industrial devices, such as motor protections, relays, rotation switches}
- H02H 1/06: Arrangements for supplying operative power {(power supply arrangements in general G05F, H02M)}
- H02H 3/02: Details
- H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H)
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

A safety test circuit includes a pulse test control circuit configured to receive a zero-vector signal and to generate a pulse test signal when the zero-vector signal is active, and first and second safety channels. The first safety channel includes a first enable circuit configured to receive the pulse test signal and a first safety input signal, and to generate a first enable signal which is active only when both the pulse test signal and the first safety input signal are inactive, and a first power signal gate configured to receive a first plurality of power control signals and to transfer the first plurality of power control signals to a power module only when the first enable signal is active. The second safety channel includes a second enable circuit configured similar to the first enable circuit, and a second power signal configured similar to the first power signal gate.

## Claims

### Claim 1

A safety test circuit, comprising:
a pulse test control circuit configured to receive a zero-vector signal and to generate a pulse test signal when the zero-vector signal is active;
a first safety channel, comprising:
a first enable circuit configured to receive the pulse test signal and a first safety input signal, and to generate a first enable signal which is active only when both the pulse test signal and the first safety input signal are inactive; and
a first power signal gate configured to receive a first plurality of power control signals and to transfer the first plurality of power control signals to a power module only when the first enable signal is active; and
a second safety channel, comprising:
a second enable circuit configured to receive the pulse test signal and a second safety input signal, and to generate a second enable signal which is active only when both the pulse test signal and the second safety input signal are inactive; and
a second power signal gate configured to receive a second plurality of power control signals and to transfer the second plurality of power control signals to the power module only when the second enable signal is active.

### Claim 2 (depends on 1)

The safety test circuit of claim 1, wherein the zero-vector signal is active when the first plurality of power control signals and the second plurality of power control signals are all at a logical zero.

### Claim 3 (depends on 2)

The safety test circuit of claim 2, wherein the zero-vector signal is a logical NOR of all the first plurality of power control signals and the second plurality of power control signals.

### Claim 4 (depends on 1)

The safety test circuit of claim 1, wherein the first power signal gate is also configured to receive an input coupled to a logical one, and to generate a first confirmation signal, wherein the first confirmation signal is a logical one while the first enable signal is active, and a logical zero while the first enable signal is inactive, and the second power signal gate is also configured to receive an input coupled to a logical one, and to generate a second confirmation signal, wherein the second confirmation signal is a logical one while the second enable signal is active, and a logical zero while the second enable signal is inactive.

### Claim 5 (depends on 4)

The safety test circuit of claim 4, wherein the first safety channel further comprises a first diagnostic circuit configured to receive the first confirmation signal, and to transmit a first error signal to the first enable circuit when the first confirmation signal is a logical one and the first enable signal is inactive, and the second safety channel further comprises a second diagnostic circuit configured to receive the second confirmation signal, and to transmit a second error signal to the second enable circuit when the second confirmation signal is a logical one and the second enable signal is inactive.

### Claim 6 (depends on 5)

The safety test circuit of claim 5, wherein the safety test circuit is configured to shut down the power module when either the first or second error signal is active.

### Claim 7 (depends on 1)

The safety test circuit of claim 1, wherein the first and second power signal gates each comprise a plurality of logical AND gates.

### Claim 8 (depends on 1)

The safety test circuit of claim 1, wherein the power module is configured to supply power to an industrial machine.

### Claim 9 (depends on 1)

The safety test circuit of claim 1, wherein the safety test circuit is implemented in an application specific integrated circuit.

### Claim 10 (depends on 1)

The safety test circuit of claim 1, wherein the pulse test control circuit is also configured to generate a pulse test signal when the zero-vector signal has remained inactive for longer than a test threshold time period.

### Claim 11 (depends on 1)

The safety test circuit of claim 1, wherein the zero-vector signal is generated by a microcontroller.

### Claim 12

A method for testing a safety circuit comprising:
receiving a zero-vector signal;
generating a pulse test signal when the zero-vector signal is active;
generating a first enable signal which is active only when both the pulse test signal and a first safety input signal are inactive;
generating a second enable signal which is active only when the pulse test signal and a second safety input signal are inactive;
transferring a first plurality of power control signals to a power module when the first enable signal is active; and
transferring a second plurality of power control signals to the power module when the second enable signal is active.

### Claim 13 (depends on 12)

The method of claim 12, wherein the zero-vector signal is active when the first plurality of power control signals and the second plurality of power control signals are all at a logical zero.

### Claim 14 (depends on 13)

The method of claim 13, wherein the zero-vector signal is a logical NOR of all the first plurality of power control signals and the second plurality of power control signals.

### Claim 15 (depends on 12)

The method of claim 12, further comprising:
receiving an input coupled to a logical one in a first power signal gate;
generating a first confirmation signal from the logical one in the first power signal gate, wherein the first confirmation signal is a logical one while the first enable signal is active, and a logical zero while the first enable signal is inactive;
receiving an input coupled to a logical one in a second power signal gate; and
generating a second confirmation signal from the logical one in the second power signal gate, wherein the second confirmation signal is a logical one while the second enable signal is active, and a logical zero while the second enable signal is inactive.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
generating a first error signal for the first power signal gate when the first confirmation signal is a logical one and the first enable signal is inactive; and
generating a second error signal for the second power signal gate when the second confirmation signal is a logical one and the second enable signal is inactive.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
shutting down the power module when either the first or second error signal is active.

### Claim 18 (depends on 15)

The method of claim 15, wherein the first and second power signal gates each comprise a plurality of logical AND gates.

### Claim 19 (depends on 12)

The method of claim 12, wherein the power module is configured to supply power to an industrial machine.

### Claim 20 (depends on 12)

The method of claim 12, further comprising:
generating a pulse test signal when the zero-vector signal has remained inactive for longer than a test threshold time period.