# US 12,597,480 B2 · Memory device, and memory system and operation method thereof

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,597,480 B2
- Document ID: US12597480B2
- Status: Granted
- Kind: B2
- Application number: 18/409,241
- Filed: 2024-01-10
- Published: 2025-03-27
- Granted: 2026-04-07
- Earliest claimed: 2023-09-25
- Assignees: Yangtze Memory Technologies Co., Ltd.
- Applicants: Yangtze Memory Technologies Co., Ltd.
- Inventors: Feiyang Zhang; Hongwen Liu
- Web page: https://patentgrep.com/patent/US12597480B2

## CPC

- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G06F 11/1012: {using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence)}
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G11C 29/789: {using non-volatile cells or latches}
- G06F 11/10: Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G11C 2029/0411: {Online error correction}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Examples of the present disclosure provide a memory device, a memory system and an operation method of the memory system, and a storage medium. The memory device includes: multiple word lines, where a plurality of strings coupled to each of the word lines are divided into a first string area and a second string area; and at least one redundant stripe corresponding to each of the word lines, where the redundant stripe comprises a first redundant stripe which is configured to store first check data. The first check data is obtainable by performing error correction coding on data in a first string area of a word line where the first redundant stripe is located and data in a second string area of a word line adjacent to the word line where the first redundant stripe is located.

## Claims

### Claim 1

A memory device, comprising:
a plurality of word lines, wherein a plurality of strings coupled to each of the word lines are divided into a first string area and a second string area, wherein the first string area and the second string area coupled to each of the word lines are located in different blocks, respectively; and
at least one redundant stripe corresponding to each of the word lines, wherein the redundant stripe comprises a first redundant stripe which is configured to store first check data, wherein the first check data is obtainable by performing error correction coding on data in a first string area of a word line where the first redundant stripe is located and data in a second string area of a word line adjacent to the word line where the first redundant stripe is located.

### Claim 2 (depends on 1)

The memory device according to claim 1, wherein the redundant stripe further comprises a second redundant stripe which is configured to store second check data, wherein the second check data is obtainable by performing error correction coding on one of data in a first string area or data in a second string area of a word line where the second redundant stripe is located.

### Claim 3 (depends on 2)

The memory device according to claim 2, comprising a 0th word line to an Nth word line numbered according to physical locations, wherein the memory device is sequentially programmed from the 0th word line to the Nth word line, and wherein N is an integer greater than 1;
the 0th word line corresponds to one second redundant stripe, and the second check data is obtainable by performing error correction coding on data in a first string area of the 0th word line;
each of the 1st to (N−1)th word lines corresponds to one first redundant stripe, and each of the first check data is obtainable by performing error correction coding on data in a first string area of a corresponding word line and data in a second string area of a preceding word line of the corresponding word line; and
the Nth word line corresponds to one first redundant stripe and one second redundant stripe, the first check data is obtainable by performing error correction coding on data in a first string area of the Nth word line and data in a second string area of the (N−1)th word line, and the second check data is obtainable by performing error correction coding on data in a second string area of the Nth word line.

### Claim 4 (depends on 3)

The memory device according to claim 3, wherein the 0th word line corresponds to a set of first start data and a set of second start data, wherein the first start data comprises data stored in a first memory cell of each string in a second string area of the 0th word line, and the second start data comprises data stored in a first memory cell of each string in the first string area of the 0th word line;
each of the 1st to (N−1)th word lines corresponds to a set of the first start data, wherein each set of the first start data comprises data stored in a first memory cell of each string in a second string area of a corresponding word line; and
the Nth word line corresponds to a set of the second start data, wherein the second start data comprises data stored in a first memory cell of each string in the second string area of the Nth word line.

### Claim 5 (depends on 2)

The memory device according to claim 2, comprising a 0th word line and a 1st word line numbered according to physical locations;
the 0th word line corresponds to one second redundant stripe, and the second check data is obtainable by performing error correction coding on data in a first string area of the 0th word line; and
the 1st word line corresponds to one first redundant stripe and one second redundant stripe, the first check data is obtainable by performing error correction coding on data in a first string area of the 1st word line and data in a second string area of the 0th word line, and the second check data is obtainable by performing error correction coding on data in a second string area of the 1st word line.

### Claim 6 (depends on 1)

The memory device according to claim 1, wherein the number of strings in the first string area is the same as the number of strings in the second string area.

### Claim 7 (depends on 6)

The memory device according to claim 6, comprising (N+1) word lines, each of the word lines is coupled to M strings, and each of the strings comprises L memory cells, and wherein
a ratio of the number of memory cells occupied by the redundant stripe to the number of memory cells is:
(
N
+
2
)
⁢
(
M
/
2
)
/
(
N
+
1
)
*
M
*
L
.

### Claim 8 (depends on 1)

The memory device according to claim 1, wherein
the first string area and the second string area coupled to each of the word lines are located in a same block.

### Claim 9

A memory system, comprising:
a memory device comprising:
a plurality of word lines, wherein a plurality of strings coupled to each of the word lines are divided into a first string area and a second string area, wherein the first string area and the second string area coupled to each of the word lines are located in different blocks, respectively; and
at least one redundant stripe corresponding to each of the word lines, wherein the redundant stripe comprises a first redundant stripe which is configured to store first check data, wherein the first check data is obtainable by performing error correction coding on data in a first string area of a word line where the first redundant stripe is located and data in a second string area of a word line adjacent to the word line where the first redundant stripe is located; and
a memory controller coupled to the memory device and configured to:
when a plurality of data errors occur in a plurality of strings coupled to one of the word lines, perform correction by using the first check data stored in a redundant stripe corresponding to a corresponding word line and the first check data stored in a redundant stripe corresponding to a word line adjacent to the corresponding word line.

### Claim 10 (depends on 9)

The memory system according to claim 9, wherein the redundant stripe further comprises a second redundant stripe which is configured to store second check data, wherein the second check data is obtainable by performing error correction coding on one of data in a first string area or data in a second string area of a word line where the second redundant stripe is located; and
the memory controller is further configured to:
when a plurality of data errors occur in a plurality of strings coupled to one of the word lines,
perform correction by using the second check data stored in a redundant stripe corresponding to a corresponding word line and the first check data stored in a redundant stripe corresponding to a word line adjacent to the corresponding word line, and
perform correction by using the first check data and the second check data stored in a redundant stripe corresponding to a corresponding word line.

### Claim 11 (depends on 10)

The memory system according to claim 10, comprising a 0th word line to an Nth word line numbered according to physical locations, wherein the memory system is sequentially programmed from the 0th word line to the Nth word line, and wherein the N is an integer greater than 1;
the 0th word line corresponds to one second redundant stripe, and the second check data is obtainable by performing error correction coding on data in a first string area of the 0th word line;
each of the 1st to (N−1)th word lines corresponds to one first redundant stripe, and each of the first check data is obtainable by performing error correction coding on data in a first string area of a corresponding word line and data in a second string area of a preceding word line of the corresponding word line; and
the Nth word line corresponds to one first redundant stripe and one second redundant stripe, the first check data is obtainable by performing error correction coding on data in a first string area of the Nth word line and data in a second string area of the (N−1)th word line, and the second check data is obtainable by performing error correction coding on data in a second string area of the Nth word line.

### Claim 12 (depends on 11)

The memory system according to claim 11, wherein the 0th word line corresponds to a set of first start data and a set of second start data, wherein the first start data comprises data stored in a first memory cell of each string in a second string area of the 0th word line, and the second start data comprises data stored in a first memory cell of each string in the first string area of the 0th word line;
each of the 1st to (N−1)th word lines corresponds to a set of the first start data, wherein each set of the first start data comprises data stored in a first memory cell of each string in a second string area of a corresponding word line; and
the Nth word line corresponds to a set of the second start data, wherein the second start data comprises data stored in a first memory cell of each string in the second string area of the Nth word line.

### Claim 13 (depends on 10)

The memory system according to claim 10, comprising a 0th word line and a 1st word line numbered according to physical locations;
the 0th word line corresponds to one second redundant stripe, and the second check data is obtainable by performing error correction coding on data in a first string area of the 0th word line; and
the 1st word line corresponds to one first redundant stripe and one second redundant stripe, the first check data is obtainable by performing error correction coding on data in a first string area of the 1st word line and data in a second string area of the 0th word line, and the second check data is obtainable by performing error correction coding on data in a second string area of the 1st word line.

### Claim 14 (depends on 9)

The memory system according to claim 9, wherein the number of strings in the first string area is the same as the number of strings in the second string area.

### Claim 15 (depends on 14)

The memory system according to claim 14, comprising (N+1) word lines, each of the word lines is coupled to M strings, and each of the strings comprises L memory cells, and wherein
a ratio of the number of memory cells occupied by the redundant stripe to the number of memory cells is:
(
N
+
2
)
⁢
(
M
/
2
)
/
(
N
+
1
)
*
M
*
L
.

### Claim 16

An operation method of a memory system, comprising:
obtaining first check data by performing error correction coding on data in a first string area coupled to a first word line where a first redundant stripe is located and data in a second string area coupled to a second word line adjacent to the first word line, wherein the first string area and the second string area coupled to each of the word lines are located in different blocks, respectively, wherein the first redundant stripe corresponds to the first word line is configured to store first the check data; and
when a plurality of data errors occur in a plurality of strings coupled to one of the word lines, performing correction by using the first check data stored in a redundant stripe corresponding to a corresponding word line and the first check data stored in a redundant stripe corresponding to a word line adjacent to the corresponding word line.

### Claim 17 (depends on 16)

The operation method according to claim 16, further comprising:
obtaining second check data by performing error correction coding on one of data in the first string area or data in the second string area of the second word line corresponding to a second redundant stripe, wherein the second redundant stripe is configured to store the second check data; and
when a plurality of data errors occur in a plurality of strings coupled to one of the word lines, performing correction by using the second check data and the first check data.

### Claim 18 (depends on 17)

The operation method according to claim 17, comprising performing correction by using the first check data and the second check data stored in a redundant stripe corresponding to a corresponding word line.

### Claim 19 (depends on 16)

The operation method according to claim 16, wherein the number of strings in the first string area is the same as the number of strings in the second string area.

### Claim 20 (depends on 16)

The operation method according to claim 16, wherein the memory system comprises (N+1) word lines, each of the word lines is coupled to M strings, and each of the strings comprises L memory cells, and wherein a ratio of the number of memory cells occupied by the redundant stripe to the number of memory cells is (N+2) (M/2)/(N+1)*M*L.