Semiconductor device
AssigneeSK hynix Inc.
InventorYoung Jun Park
Life of this patent
Estimating the term…
Abstract
A semiconductor chip includes a command address input circuit configured to generate a rising command address and a falling command address by receiving an external command address and configured to output the rising command address and the falling command address to a through electrode, and a test circuit configured to generate a detection signal by latching a remaining one of the rising command address and the falling command address as any one of the rising command address and the falling command address and configured to detect a fail in the transmission of the rising command address and the falling command address by detecting the logic level of the detection signal.
Claims20
A semiconductor chip comprising:
- a command address input circuit configured to receive an external command address to generate a rising command address and a falling command address and configured to output the rising command address and the falling command address to a through electrode;
- and
- a test circuit configured to generate a detection signal by latching a remaining one of the rising command address and the falling command address as any one of the rising command address and the falling command address that are output in synchronization with rising and falling clock signals and configured to detect a fail in a transmission of the rising command address and the falling command address by detecting a logic level of the detection signal.
A semiconductor chip comprising:
- a command address input circuit configured to generate first and second rising command addresses and first and second falling command addresses by receiving first to fourth external command addresses and configured to output the first and second rising command addresses and the first and second falling command addresses to a through electrode;
- and
- a test circuit configured to generate first and second detection signals by latching a remaining one of the first and second rising command addresses and the first and second falling command addresses as any one of the first and second rising command addresses and the first and second falling command addresses that are output in synchronization with rising and falling clock signals and configured to detect a fail in a transmission of the first and second rising command addresses and the first and second falling command addresses when the first and second detection signals are different from a set value.
Dependencies are inferred from the claim text.