Memory device

A memory device, comprising:

• a word line selector configured to select word lines;
• a memory cell having cells that are connected to the word lines and to bit line units so as to be arrayed in a matrix;
• a bit detector configured to detect, via the bit line units, logic values of bit data stored in cells connected to a selected word line;
• a data output circuit configured to output data based on results of detection by the bit detector;
• and
• a controller,
• wherein
• the memory cell has a standard area and a fixed area, with a plurality of fixed values stored across the standard area and the fixed area,
• the standard area includes a first normal area and a first ROM area, with a first portion of the plurality of fixed values stored in the first ROM area,
• the fixed area includes a second normal area and a second ROM area, with a second portion of the plurality of fixed values stored in the second normal area and the second ROM area, wherein the fixed area is dedicated to fixed value storage,
• the controller is configured to compare each fixed value read from the standard area and the fixed area in the memory cell via the bit detector and the data output circuit, with a respective expected value, and
• determine that a peripheral circuit around the memory cell is normal, based on all fixed values from the standard area and the fixed area matching respective expected values, and
• read data out from the first normal area in the standard area.