Detection of leakage current in flash memory

A memory system, comprising:

• a memory device, comprising:
• a memory cell array, wherein the memory cell array comprises one or more planes of memory cells;
• and
• a leakage detection circuit coupled with the memory cell array, wherein the leakage detection circuit is configured to output a signal to indicate whether a leakage current exists in the memory cell array, and wherein the leakage detection circuit comprises a logic and a resistor circuit, the resistor circuit comprises a first end coupled to a pump source and a second end coupled to a global word line, and the logic comprises a first input coupled to the first end of the resistor circuit and a second input coupled to the global word line, wherein the resistor circuit comprises a plurality of selectable resistors, each corresponding to a respective transistor, and the logic is configured to compare a voltage across a selected combination of the plurality of selectable resistors to a preset threshold during a program operation, and to output the signal if the voltage exceeds the preset threshold during a programming phase and after a variation of a current of the global word line during a preset period of time is less than a preset value;
• and
• a controller coupled to the memory device, wherein the controller is configured to perform operations comprising:
• initiating a program operation for the memory cell array;
• receiving a first signal from the logic of the leakage detection circuit, the first signal indicating that the leakage current exists in a word line in the memory cell array, the word line being coupled to the global word line;
• in response to receiving the first signal, determining that the leakage current exists in a first block of the memory cell array, the first block comprising the word line;
• and
• marking the first block as not usable.

A method for operating a memory device, comprising:

• performing a program operation of the memory device;
• and
• performing a leakage detection during a programming phase in the program operation and after a variation of a current of a global word line during a preset period of time is less than a preset value;
• wherein performing the leakage detection comprises:
• comparing a voltage over a combination of one or more resistors of a resistor circuit with a preset threshold during the program operation by a logic, wherein the resistor circuit comprises a first end coupled to a pump source and a second end coupled to the global word line in the memory device, and the logic has a first input coupled to the first end of the resistor circuit and a second input coupled to the global word line;
• determining that the voltage is larger than or equal to the preset threshold;
• and
• in response to determining that the voltage is larger than or equal to the preset threshold, outputting a signal indicating that a leakage current exist in a word line coupled to a memory cell in the memory device, the word line being coupled to the global word line.