Selectively erasing one of multiple erase blocks coupled to a same string using gate induced drain leakage

A method for performing an erase operation on a memory array comprising a first erase block and a second erase block that are coupled to one or more first strings, the method comprising:

• applying a voltage having a first value to a sense line to selectively erase the second erase block independently of the first erase block to generate gate induced drain leakage (GIDL) holes at one or more select transistors coupled to the sense line, wherein:
• the first erase block comprises a first group of memory cells coupled to a first group of access lines and the one or more first strings;
• and
• the second erase block comprises a second group of memory cells coupled to a second group of access lines and the one or more first strings, wherein:
• the first group of access lines and the second group of access lines are separated by dummy access lines;
• and
• the first group of access lines are located between the sense line and the dummy access lines;
• applying a voltage having a second value less than the first value to the first group of access lines to carry the GIDL holes through the first group of access lines while retaining data stored on the first erase block;
• and
• applying a voltage having a third value less than the second value to the second group of memory cells to reduce a threshold voltage level of the second group memory cells.

An apparatus, comprising:

• a memory array comprising a plurality of physical blocks of memory cells, each physical block of memory cells of the plurality of physical blocks comprising a plurality of strings of memory cells, wherein a first string of the plurality of strings corresponds to multiple erase blocks of a particular physical block that are erasable at different times, and wherein the first string comprises:
• a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block of the multiple erase blocks;
• a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block;
• and
• a first number of dummy access lines separating the first group of access lines from the second group of access lines;
• and
• a controller coupled to the memory array and configured to, in order to selectively erase the second erase block independently of the first erase block:
• apply a voltage having a first value to a sense line to generate gate induced drain leakage (GIDL) holes;
• apply a voltage having a second value less than the first value to the first group of access lines to carry the GIDL holes through the first group of access lines and retain data stored on the first erase block;
• and
• apply a voltage having a third value less than the second value to the second group of access lines to reduce a threshold voltage level of the second group of memory cells.