Non-volatile memory and corresponding manufacturing method
OwnerRadouane Habhab, Vincenzo Della Marca +4inventors
InventorsRadouane Habhab, Vincenzo Della Marca, Nadia Miridi ép Seroschtanoff, Pascal Masson, Franck Melul, Madjid Akbal
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Abstract
The non-volatile memory device includes memory cells including a control gate vertically buried in a semiconductor substrate doped with a first type of dopant and a dielectric interface able to trap electrical charges covering sides of the control gate facing the semiconductor substrate. The device furthermore includes a vertical implanted region of a second type of dopant opposite to the first type located along the sides of the control gate in the semiconductor substrate.
Claims20
A non-volatile memory device comprising:
- memory cells including
- a control gate vertically buried in a semiconductor substrate doped with a first type of dopant,
- a dielectric interface able to trap electrical charges covering sides of the control gate facing the semiconductor substrate, and
- a vertical implanted region of a second type of dopant opposite to the first type located along the sides of the control gate in the semiconductor substrate.
A non-volatile memory device comprising:
- memory cells including
- a control gate vertically buried in a semiconductor substrate doped with a first type of dopant,
- a dielectric interface able to trap electrical charges covering sides of the control gate facing the semiconductor substrate, and
- a vertical implanted region of a second type of dopant opposite to the first type located along the sides of the control gate in the semiconductor substrate;
- and
- a writing circuit configured to generate deletion conditions adapted to an injection of hot charge carriers of a first sign into the dielectric interface, from the vertical implanted region as a source of charge carriers of the first sign.
A method for manufacturing a non-volatile memory device including memory cells, the manufacture of each memory cell comprising:
- a formation of a control gate vertically buried in a semiconductor substrate doped with a first type of dopant;
- a formation of a dielectric interface able to trap electrical charges covering sides of the control gate facing the semiconductor substrate;
- and furthermore
- a formation of a vertical implanted region of a second type of dopant opposite to the first type located along the sides of the control gate in the semiconductor substrate.
Dependencies are inferred from the claim text.