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US 12,597,470 B2Granted
Architecture and method for NAND memory operation
AssigneeYangtze Memory Technologies Co., Ltd.
InventorChanghyun Lee
Life of this patent
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Abstract
In a method for programming a memory cell string, a programming voltage is applied on a selected word line to program a selected memory cell of the memory cell string. A first pass voltage is applied on a first word line coupled to a first memory cell of the memory cells. A second pass voltage is applied on a second word line coupled to a second memory cell of the memory cells. Further, a third pass voltage is applied on a third word line coupled to a third memory cell of the memory cells. The first, second and third memory cells are located at a first side of the selected memory cell in the memory cell string, and the second memory cell is disposed between the first memory cell and the third memory cell. The second pass voltage is higher than the first pass voltage and the third pass voltage.
Claims20
A method for programming memory cells of a memory cell string in a memory device, the method comprising:
- applying a programming voltage on a selected word line to program a selected memory cell of the memory cells, the selected memory cell having a gate terminal coupled to the selected word line;
- applying a first pass voltage on a first word line coupled to a first memory cell of the memory cells located at a first side of the selected memory cell in the memory cell string;
- applying a second pass voltage on a second word line coupled to a second memory cell of the memory cells located at the first side of the selected memory cell in the memory cell string;
- applying a third pass voltage on a third word line coupled to a third memory cell of the memory cells located at the first side of the selected memory cell in the memory cell string, the second pass voltage being higher than the first pass voltage and the third pass voltage, and the second memory cell being disposed between the first memory cell and the third memory cell;
- and
- applying an interface pass voltage on a first interface word line coupled to a first interface memory cell that is located at the first side of the selected memory cell and disposed between the second memory cell and the third memory cell,
- wherein:
- the interface pass voltage is in a range between the second pass voltage and the third pass voltage.
5 more elements
A memory device, comprising:
- a memory cell string formed of memory cells including a selected memory cell;
- a voltage generator coupled to the memory cell string;
- and
- a controller configured to:
- apply a programming voltage generated by the voltage generator through an address decoding circuit on a selected word line for programing the selected memory cell of the memory cells, the selected memory cell having a gate terminal coupled to the selected word line;
- apply a first pass voltage generated by the voltage generator through the address decoding circuit on a first word line coupled to a first memory cell of the memory cells located at a first side of the selected memory cell in the memory cell string;
- apply a second pass voltage generated by the voltage generator through the address decoding circuit on a second word line coupled to a second memory cell of the memory cells located at the first side of the selected memory cell in the memory cell string;
- apply a third pass voltage generated by the voltage generator through the address decoding circuit on a third word line coupled to a third memory cell of the memory cells located at the first side of the selected memory cell in the memory cell string, the second pass voltage being higher than the first pass voltage and the third pass voltage, and the second memory cell being disposed between the first memory cell and the third memory cell;
- and
- apply an interface pass voltage generated by the voltage generator through the address decoding circuit on a first interface word line coupled to a first interface memory cell that is located at the first side of the selected memory cell and disposed between the second memory cell and the third memory cell,
- wherein:
- the interface pass voltage is in a range between the second pass voltage and the third pass voltage.
9 more elements
A memory system device, comprising:
- a plurality of memory devices;
- master control circuitry coupled with the plurality of memory devices and configured to operate one or more memory devices of the plurality of memory devices for data generation and data transfer;
- and
- interface circuitry coupled with the master control circuitry and configured to transfer data between the master control circuitry and an external device, wherein a memory device of the plurality of memory devices includes:
- a memory cell string formed of memory cells including a selected memory cell;
- a voltage generator coupled to the memory cell string;
- and
- a controller configured to:
- apply a programming voltage generated by the voltage generator through an address decoding circuit on a selected word line for programing the selected memory cell of the memory cells, the selected memory cell having a gate terminal coupled to the selected word line;
- apply a first pass voltage generated by the voltage generator through the address decoding circuit on a first word line coupled to a first memory cell of the memory cells located at a first side of the selected memory cell in the memory cell string;
- apply a second pass voltage generated by the voltage generator through the address decoding circuit on a second word line coupled to a second memory coll of the memory cells located at the first side of the selected memory cell in the memory cell string;
- apply a third pass voltage generated by the voltage generator through the address decoding circuit on a third word line coupled to a third memory cell of the memory cells located at the first side of the selected memory cell in the memory cell string, the second pass voltage being higher than the first pass voltage and the third pass voltage, and the second memory cell being disposed between the first memory cell and the third memory cell;
- and
- apply an interface pass voltage generated by the voltage generator through the address decoding circuit on a first interface word line coupled to a first interface memory cell that is located at the first side of the selected memory cell and disposed between the second memory cell and the third memory cell,
- wherein:
- the interface pass voltage is in a range between the second pass voltage and the third pass voltage.
13 more elements
Dependencies are inferred from the claim text.