US 12,597,468 B2 · Three-dimensional memory devices and fabricating methods thereof

Abstract

Three-dimensional (3D) memory devices and fabricating methods are disclosed. A disclosed 3D memory device can comprises, a first semiconductor structure comprising an array of first type memory cells, a second semiconductor structure comprising an array of second type memory cells different from the first type memory cells, a third semiconductor structure comprising a first peripheral circuit, and a fourth semiconductor structure comprising a second peripheral circuit. The third semiconductor structure and the fourth semiconductor structure are sandwiched between the first semiconductor structure and the second semiconductor structure in a vertical direction.

Claims20

Dependent claims

A three-dimensional (3D) memory device, comprising:

a first semiconductor structure comprising an array of first type memory cells;
a second semiconductor structure comprising an array of dynamic flash memory cells different from the first type memory cells;
a third semiconductor structure comprising a first peripheral circuit;
and
a fourth semiconductor structure comprising a second peripheral circuit;
wherein the third semiconductor structure and the fourth semiconductor structure are sandwiched between the first semiconductor structure and the second semiconductor structure in a vertical direction.

3 more elements

A system, comprising:

a memory device configured to store data, and comprising:
a first semiconductor structure comprising an array of first type memory cells,
a second semiconductor structure comprising an array of dynamic flash memory cells different from the first type memory cells,
a third semiconductor structure comprising a first peripheral circuit, and
a fourth semiconductor structure comprising a second peripheral circuit,
wherein the third semiconductor structure and the fourth semiconductor structure are sandwiched between the first semiconductor structure and the second semiconductor structure in a vertical direction;
and
a memory controller coupled to the memory device and configured to control the array of first type memory cells and the array of dynamic flash memory cells through the first peripheral circuit and the second peripheral circuit.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application

18/095,336Filed 10 Jan 2023 · continuation

Priority

22 Dec 2022

Published

US 2024/0212753 A127 Jun 2024

Granted

7 Apr 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification16 codes

G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
H10B 80/00
Assemblies of multiple devices comprising at least one memory device covered by
H10B 41/10
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the top-view layout
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels

Three-dimensional memory devices and fabricating methods thereof

Life of this patent

Three-dimensional memory devices and fabricating methods thereof

Life of this patent

Abstract

Claims20