Back to results
US 12,597,467 B2Granted
Adaptive memory management and control circuitry
AssigneeNumem Inc.
InventorsEric Hall, Doug Smith, Nicholas T. Hendrickson, Jack Guedj
Life of this patent
Estimating the term…
Abstract
An adaptive memory management and control circuitry (AMMC) to provide extended test, performance, and power optimizing capabilities for a resistive memory is disclosed herein. In one embodiment, a resistive memory comprises a resistive memory array and an Adaptive Memory Management and Control circuitry (AMMC) that is coupled to the resistive memory array. The AMMC is configured with extended test, reliability, performance and power optimizing capabilities for the resistive memory.
Claims20
Resistive memory comprising:
- a resistive memory array;
- and
- an adaptive Memory Management and Control circuitry (AMMC) coupled to the resistive memory array, wherein the AMMC is configured with extended test, reliability, performance or power optimizing capabilities, wherein the AMMC is configured with the power optimizing capabilities by having a first region of the resistive memory array active and having a second region of the resistive memory in a low power mode.
A memory subsystem comprising:
- a smart compute memory circuitry;
- a resistive memory array coupled to the smart compute memory circuitry;
- and
- an Adaptive Memory Management and Control circuitry (AMMC) coupled to the resistive memory array, wherein the AMMC is configured with the power optimizing capabilities by having a first region of the resistive memory array active and having a second region of the resistive memory in a low power mode.
1 more element
Resistive memory comprising:
- a resistive memory array;
- and
- an adaptive Memory Management and Control circuitry (AMMC) coupled to the resistive memory array, wherein the AMMC is configured with a performance optimization mode to improve performance by reading from or writing to multiple memory banks of the resistive memory either sequentially or with a set addressing sequence enabling to read from or write to a second memory bank while a read or write settles in a first memory bank of the resistive memory.
Dependencies are inferred from the claim text.