Semiconductor memory devices with differential threshold voltages
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMeng-Sheng Chang, Chia-En Huang, Yih Wang
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Abstract
A memory device includes at least a non-volatile memory cell. The non-volatile memory cell includes a resistor with a variable resistance, a first transistor, and a second transistor that are coupled in series. The first transistor has a first threshold voltage and the second transistor has a second threshold voltage that is different from the first threshold voltage. The first and the second transistors have their channels doped in respective different concentrations.
Claims20
A memory device, comprising:
- a non-volatile memory cell;
- wherein the non-volatile memory cell includes a resistor with a variable resistance, a first transistor, and a second transistor that are coupled in series;
- wherein the first transistor has a first threshold voltage and the second transistor has a second threshold voltage that is different from the first threshold voltage;
- and
- wherein the first and the second transistors have their channels doped in respective different concentrations.
A memory device, comprising:
- a plurality of resistive memory cells commonly connected between a bit line (BL) and a source line (SL);
- wherein each of the resistive memory cells includes a resistor, a first transistor, and a second transistor coupled to each other in series, with the resistor connected to the BL and the second transistor connected to the SL;
- and
- wherein the first transistor and the second transistor have different work function layers.
A method for accessing a memory device, comprising:
- providing a plurality of memory cells coupled between a bit line (BL) and a source line (SL), wherein each of the plurality of memory cells comprises a resistor operatively coupled to the BL, a first transistor connected to the resistor in series, and a second transistor connected to the first transistor in series and operatively coupled to the SL;
- and
- reading one of the plurality of memory cells includes asserting one of a plurality of word lines (WLs) that gates the first and second transistors of the memory cell.
Dependencies are inferred from the claim text.