SRAM with PUF dedicated sector standing-by

A static random access memory device comprising a memory array provided with SRAM memory cells, each of said cells of said array comprising a first storage node and a second storage node, the static random access memory device being further provided with a control circuit for controlling said cells configured to, during a power-up phase of the array, place a first set of cells located in a first zone of the array in an undetermined so-called “metastable” state in which their respective first storage node and their second storage node are placed to equal or substantially equal potentials, while a second set of cells located in a second zone of the array distinct from the first zone are initialized in a determined state in which their respective first node and second node are at different respective potentials between a low state, corresponding in particular to a given logic state ‘0’, and a high state, corresponding to a complementary logic state ‘1’, then subsequent to this power-up phase, place the array into a first operating mode in which the first set of cells of the first zone is kept in the “metastable” state while the cells of the second zone are kept accessible for reading and writing.