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US 12,597,463 B2Granted
Techniques to map and access column read enabled memory
AssigneeIntel Corporation
InventorsSourabh Dongaonkar, Chetan Chauhan, Jawad B. Khan, Rajesh Sundaram, Sandeep K. Guliani
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Abstract
Column read enabled three dimensional cross-point memory is optimized to reduce delay time due to partition busy times incurred when reading from a same partition. A column read enabled memory media stores each entry of a logical column of an array of bits in contiguous different physical rows and different physical columns of the cross-point memory array than any other entry of the logical column. Subsets of the contiguous different physical rows are stored in different partitions to reduce the delay time incurred when performing column reads from a same partition to improve media management operation performance.
Claims13
A memory device comprising:
- a memory array to have a plurality of memory cells maintained in a plurality of memory dies, the plurality of memory dies arranged such that each memory cell is addressable based on a physical row and a physical column address;
- and
- circuitry to:
- map groups of two or more physical column addresses to separate multi-bit logical columns such that a respective multi-bit logical column is arranged so that each bit of data included in the respective multi-bit logical column is stored to a different physical row and physical column address of the memory array than any other bits of data included in the respective multi-bit logical column;
- map an input partition component to a partition offset programmed to separate memory dies of the plurality of memory dies, the input partition mapped to the partition offset to determine a partition from among multiple partitions for the separate memory dies;
- receive a system address having offset information that indicates the partition is to be accessed and also indicates which memory die from among the plurality of memory dies is to be accessed;
- and
- access data included in at least one multi-bit logical column from among the separate multi-bit logical columns based on the system address and the offset information.
5 more elements
A system comprising:
- a processor;
- and
- a memory subsystem operatively connected to the processor, the memory subsystem to include:
- a memory array to have a plurality of memory cells maintained in a plurality of memory dies, the plurality of memory dies arranged such that each memory cell is addressable based on a physical row and a physical column address;
- and
- circuitry to:
- map groups of two or more physical column addresses to separate multi-bit logical columns such that a respective multi-bit logical column is arranged so that each bit of data included in the respective multi-bit logical column is stored to a different physical row and physical column address in the memory array than any other bit of data included in the respective multi-bit logical column;
- map an input partition component to a partition offset programmed to separate memory dies of the plurality of memory dies, the input partition mapped to the partition offset to determine a partition from among multiple partitions for the separate memory dies;
- receive a system address having offset information that indicates the partition is to be accessed and also indicates which memory die from among the plurality of memory dies is to be accessed;
- and
- access data included in at least one multi-bit logical column from among the separate multi-bit logical columns based on the system address and the offset information.
8 more elements
A method comprising:
- partitioning a memory array into multiple partitions, the memory array having a plurality of memory cells maintained in a plurality of memory dies, the plurality of memory dies arranged such that each memory cell is addressable based on a physical row and a physical column address;
- mapping groups of two or more physical column addresses to separate multi-bit logical columns such that a respective multi-bit logical column is arranged so that each bit of data included in the respective multi-bit logical column is stored to a different physical row and physical column address of the memory array than any other bit of data included in the respective multi-bit logical column;
- mapping an input partition component to a partition offset programmed to separate memory dies of the plurality of memory dies, the input partition mapped to the partition offset to determine a partition from among multiple partitions for the separate memory dies;
- receiving a system address having offset information that indicates the partition is to be accessed and also indicates which memory die from among the plurality of memory dies is to be accessed;
- and
- accessing data included in at least one multi-bit logical column from among the separate multi-bit logical columns based on the system address and the offset information.
3 more elements
Dependencies are inferred from the claim text.