Non-volatile memory with hybrid routing for shared word line switches

A non-volatile storage apparatus, comprising:

• a first semiconductor die comprising a first non-volatile memory array and a second non-volatile memory array adjacent to the first non-volatile memory array, the first non-volatile memory array comprises a first plurality of non-volatile memory cells and word lines connected to the first plurality of non-volatile memory cells, the second non-volatile memory array comprises a second plurality of non-volatile memory cells and word lines connected to the second plurality of non-volatile memory cells, the first semiconductor die further comprises a first plurality of pathways connected to the first non-volatile memory array and the second non-volatile memory array;
• and
• a second semiconductor die attached to the first semiconductor die, the second semiconductor die comprising a control circuit and a second plurality of pathways, the first plurality of pathways are in communication with the second plurality of pathways, the control circuit is configured to transfer signals to the first plurality of non-volatile memory cells and the second plurality of non-volatile memory cells via the first plurality of pathways and the second plurality of pathways, the control circuit comprises:
• one or more voltage sources;
• and
• word line switches connected to the one or more voltage sources, a first subset of the word line switches are connected to a first set of word lines of the first non-volatile memory array and a second set of word lines of the second non-volatile memory array via routing within one or more of the second plurality of pathways in a direction from between the first non-volatile memory array and the second non-volatile memory array toward one or more of the first non-volatile memory array and the second non-volatile memory array, a second subset of the word line switches are connected to a third set of word lines of the first non-volatile memory cell array and a fourth set of word lines of the second non-volatile memory cell array via routing within one or more of the second plurality of pathways in a direction from between the first non-volatile memory array and the second non-volatile memory array toward one or more of the first non-volatile memory array and the second non-volatile memory array.

A method, comprising:

• transmitting signals from a first subset of word line switches to a first set of word lines of a first non-volatile memory array and a second set of word lines of a second non-volatile memory array adjacent to the first non-volatile memory array via routing within one or more low metal layers in a lateral direction from between the first non-volatile memory array and the second non-volatile memory array toward one or more of the first non-volatile memory array and the second non-volatile memory array;
• transmitting signals from a second subset of word line switches to a third set of word lines of the first non-volatile memory array and a fourth set of word lines of the second non-volatile memory array within one or more high metal layers in the lateral direction, the one or more low metal layers are positioned above the word line switches, the one or more high metal layers are positioned above the one or more low metal layers, the one or more high metal layers are positioned below the first non-volatile memory structure and the second non-volatile memory structure;
• transmitting signals from a third subset of word line switches to a fifth set of word lines of the first non-volatile memory array without transmitting signals from the third subset of word line switches to word lines of the second non-volatile memory array;
• and
• transmitting signals from a fourth subset of word line switches to a sixth set of word lines of the second non-volatile memory array without transmitting signals from the fourth subset of word line switches to word lines of the first non-volatile memory array.