Apparatuses and methods for row hammer counter mat
AssigneeMicron Technology, Inc.
InventorsYuan He, Dong Pan
Life of this patent
Estimating the term…
Abstract
Apparatuses and methods for row hammer counter mat. A memory array may have a number of memory mats and a counter memory mat. The counter mat stores count values, each of which is associated with a row in one of the other memory mats. When a row is accessed, the count value is read out, changed, and written back to the counter mat. In some embodiments, the count value may be processed within access logic of the counter mat, and a row hammer flag may be provided to the bank logic. In some embodiments, the counter mat may have a folded architecture where each sense amplifier is coupled to multiple bit lines in the counter mat. The count value may be used to determine if the accessed row is an aggressor so that its victims can be refreshed as part of a targeted refresh.
Claims11
An apparatus comprising:
- a first memory mat comprising a first plurality of word lines;
- a second memory mat comprising a second plurality of memory cells configured to store a plurality of count values, each associated with one of the plurality of word lines;
- a row decoder comprising a mapping engine configured to receive a row address associated with one of the plurality of word lines and generate a counter address associated with the associated one of the plurality of count values, wherein the counter address includes a counter row address and a counter column which are used to activate rows and columns of the second memory mat to access the associated one of the plurality of count values;
- and
- a plurality of access logic circuits each associated with one of the plurality of count values, wherein when activated based on the counter address, an activated one of the plurality of access logic circuits is configured to update the associated one of the plurality of count values and provide a row hammer flag at an active level if the updated one of the plurality of count values meets or exceeds a threshold.
An apparatus comprising:
- a first memory mat comprising a first word line and a second word line;
- a second memory mat comprising a third word line, a first set of bit lines and a second set of bit lines, a first set of memory cells configured to store a first count value that represents a number of accesses to the first word line disposed at the intersection of the third word line and the first set of bit lines, and a second set of memory cells configured to store a second count value that represents a number of accesses to the second word line disposed at the intersection of the third word line and the second of bit lines;
- and
- a mapping engine configured to receive a row address corresponding to the first word line or corresponding to second word line and generate a counter address which specifies the third word line and the first set of memory cells that store the first count value when the row address corresponds to the first word line and which specifies the third word line and the second set of memory cells that store the second count value when the row address corresponds to the second word line.
Dependencies are inferred from the claim text.