Write leveling in DDR memory device and operating method thereof

A storage device, comprising:

• a memory controller;
• a write leveling system, comprising:
• a frequency divider, arranged to receive a clock signal from the memory controller, and perform frequency dividing operation upon the clock signal to generate multiple frequency-divided clock signals;
• a signal processing circuit, arranged to receive a data strobe signal from the memory controller, and perform signal processing upon the data strobe signal to generate multiple processed data strobe signals;
• a data control circuit, arranged to generate a data signal according to the multiple frequency-divided clock signals and the multiple processed data strobe signals;
• and
• a data pin, arranged to receive the data signal from the data control circuit, and transmit the data signal to the memory controller, wherein the memory controller determines whether to delay the data strobe signal according to the data signal;
• wherein the multiple processed data strobe signals comprise a first processed data strobe signal and a second processed data strobe signal;
• the data strobe signal has a first rising edge and a second rising edge;
• one of the first processed data strobe signal and the second processed data strobe signal is generated in response to the first rising edge of the data strobe signal;
• a first rising edge of said one of the first processed data strobe signal and the second processed data strobe signal aligns with the first rising edge of the data strobe signal;
• another of the first processed data strobe signal and the second processed data strobe signal is generated in response to the second rising edge of the data strobe signal;
• and a first rising edge of said another of the first processed data strobe signal and the second processed data strobe signal aligns with the second rising edge of the data strobe signal.