Read circuit and memory system
AssigneeNational University Corporation Shizuoka University
InventorToru Tanzawa
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AssigneeNational University Corporation Shizuoka University
InventorToru Tanzawa
Estimating the term…
A control circuit that reads data from a memory array including a bit line electrically connecting memory cells, includes an amplification unit that includes a read line connected to the bit line, charges the bit line via the read line during a read operation of the data, and then amplifies an electric signal of the bit line at a sense node on the read line, and an inverter that determines data stored in a memory cell selected during the data read operation on the basis of a voltage of the sense node, in which the amplification unit includes switching elements, the switching element charges the bit line on the basis of power supplied from a first power supply having a first voltage, and the switching element is turned on/off on the basis of power supplied from a second power supply having a second voltage higher than the first voltage.
A read circuit configured to read data from a memory array including a plurality of bit lines, each of the bit lines being a line-shaped wiring section electrically connecting a plurality of memory cells, the read circuit comprising:
Dependencies are inferred from the claim text.