Operating method of electronic device including processor executing semiconductor layout simulation module based on machine learning

A method of generating layout image using an electronic device which includes a processor configured to execute a semiconductor layout simulation module based on machine learning, the method comprising:

• receiving, at the semiconductor layout simulation module, a target wafer image, the target wafer image including a target pattern to be patterned in a semiconductor integrated circuit;
• and
• generating a layout image using a density image and the target wafer image as inputs for the semiconductor layout simulation module,
• wherein the density image is wider than the target wafer image and includes information about a density of patterns of a region which includes the target wafer image.

A method of confirming a semiconductor layout using an electronic device which includes a processor configured to execute a semiconductor layout simulation module based on machine learning, the method comprising:

• receiving, at the semiconductor layout simulation module, a target wafer image;
• generating a layout image using, as inputs for the semiconductor layout simulation module, the target wafer image and at least one of a density image and a fabrication device information image of a semiconductor integrated circuit fabricated by a semiconductor fabrication device based on a first final layout image;
• generating a wafer image based on the layout image and at least one of the fabrication device information image and the density image;
• determining whether the wafer image is acceptable based on a comparison of the wafer image and the target wafer image;
• adjusting the layout image when the wafer image is not acceptable;
• confirming the layout image as a second final layout image when the wafer image is acceptable;
• and
• fabricating a semiconductor integrated circuit based on the confirmed layout image,
• wherein the density image includes information about a density of patterns of a region which includes the layout image and is wider than the layout image.