Determining IR drops for circuit networks using Barycenter model

A method comprising:

• providing a system graph of an electronic circuit comprising multiple instances of at least one primitive;
• identifying at least one branch of the system graph as at least one of a tree branch or a link, wherein the tree branches form a tree of the system graph;
• dividing the tree into n subtree instances comprising at least first and second subtree instances, wherein n is a predefined number of instances having an integer value 2 or greater;
• identifying links of the system graph as at least one of a global link or a local link, wherein the system graph comprises both global and local links, a global link forms a path from a branch of the first subtree instance to a branch of the second subtree instance, and a loop with the global link and branches of the first and second subtrees has a voltage drop of 0;
• using at least one computer processor, partitioning the first subtree instance into i subtrees while a number of branches of at least one of the i subtrees is greater than a predefined partition size;
• modeling at least one of the i subtrees using a block model, wherein the block model comprises:
• an internal point node, which is a boundary node of the block model;
• a plurality of boundary nodes which are not the internal point node of the block model;
• a plurality of boundary branches, one boundary branch coupling to at least one boundary node, which is not the internal point node, to the internal point node;
• using the block model, determining a current-resistance (IR) drop for at least one branch of the tree of the system graph;
• and
• outputting on a user display one or more of the IR drops to allow the user to view and make updates before fabrication of the electronic circuit.

A method comprising:

• using at least one computer processor, partitioning a system graph of an electronic circuit design into a plurality of subcells while a number of branches in at least one of the subcells is greater than a predefined partition size, wherein subcells at a lowest level in a tree of the system graph are referred to as primitive cells;
• converting at least one of the subcells into corresponding model blocks, a model block having only one node to which at least one boundary node of the model block is directly coupled to;
• determining initial value solutions for primitive cells using model blocks for the primitive cells;
• determining boundary conditions for the subcells;
• using the determined initial value solutions for the primitive cells, calculating initial value solutions for at least one subcell from a bottom to a top of the assembled structure;
• using the block models, determining a current-resistance (IR) drop for at least one branch of the tree of the system graph;
• and
• displaying one or more of the IR drops before fabrication of the electronic circuit.