Efficient delay calculations in replicated designs
AssigneeCadence Design Systems, Inc.
InventorsIgor Keller, Nikita Sergeev, Pradeep Yadav, Maksim Baranov
Life of this patent
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Abstract
Disclosed is an improved approach to implement sharing of delay calculations for replicated portions of a design, where input slews may be different between those replicated design portions. This allows the system to experience runtime improvements for timing analysis of electronic designs.
Claims20
A method for processing an electronic design, comprising:
- receiving the electronic design;
- identifying sibling portions within the electronic design;
- identifying a dependency between a first sibling portion and a second sibling portion of the electronic design;
- breaking the dependency between the first sibling portion and the second sibling portion of the electronic design;
- and
- sharing a delay calculation between the first sibling portion and the second sibling portion of the electronic design.
A computer program product that includes a non-transitory computer readable medium, the non-transitory computer readable medium comprising a plurality of computer instructions which, when executed by a processor, cause the processor to execute performing a process for processing an electronic design, the process comprising:
- receiving the electronic design;
- identifying sibling portions within the electronic design;
- identifying a dependency between a first sibling portion and a second sibling portion of the electronic design;
- breaking the dependency between the first sibling portion and the second sibling portion of the electronic design;
- and
- sharing a delay calculation between the first sibling portion and the second sibling portion of the electronic design.
A system for processing an electronic design, comprising:
- a memory comprising a storage structure to store a plurality of instructions;
- and
- a processor, wherein the processor is configured to execute the plurality of instructions to process the electronic design by receiving the electronic design;
- identifying sibling portions within the electronic design;
- identifying a dependency between a first sibling portion and a second sibling portion of the electronic design;
- breaking the dependency between the first sibling portion and the second sibling portion of the electronic design;
- and sharing a delay calculation between the first sibling portion and the second sibling portion of the electronic design.
Dependencies are inferred from the claim text.