Systems and methods for hardware acceleration of masking and normalizing data with a triangular input mask

Computer storage media storing a configuration file, the configuration file specifying a configuration of a field programmable gate array (FPGA) comprising a configurable interconnect fabric and a plurality of logic blocks, where an FPGA configured based on the configuration file comprises logic blocks, connected by the configurable interconnect fabric, implementing a mask-normalize circuit comprising a data normalization circuit, the mask-normalize circuit being configured to:

• receive input data including data values organized into rows and columns at a plurality of indices of the input data, each row having N data values;
• select, by a first local masking block, R[i] unmasked data values of a row of the input data in accordance with a mask and an index i of the row;
• select, by a second local masking block, N−R[i] unmasked data values of another row of the input data in accordance with the mask and an index of the another row;
• merge the R[i] unmasked data values of the row and the N−R[i] data values of the another row to form a combined data vector of N data values;
• and
• compute, by the data normalization circuit comprising a first accumulator and a second accumulator:
• R[i] normalized values based on the R[i] unmasked data values in a first sub-vector of the combined data vector, wherein the data normalization circuit accumulates, in the first accumulator, a first denominator based on the R[i] unmasked data values of the first sub-vector and computes the R[i] normalized values based on the first denominator;
• and
• N−R[i] normalized values based on the N−R[i] data values of a second sub-vector of the combined data vector to generate a combined normalized data vector of N normalized data values, wherein the data normalization circuit accumulates, in the second accumulator, a second denominator based on the N−R[i] unmasked data values of the second sub-vector and computes the N−R[i] normalized values based on the second denominator.

A field programmable gate array (FPGA) comprising a configurable interconnect fabric connecting a plurality of logic blocks, the configurable interconnect fabric and the logic blocks being configured to implement a mask-normalize circuit comprising a data normalization circuit, the mask-normalize circuit being configured to:

• receive input data including data values organized into rows and columns at a plurality of indices of the input data, each row having N data values;
• select, by a first local masking block, R[i] unmasked data values of a row of the input data in accordance with a mask and an index i of the row;
• select, by a second local masking block, N−R[i] unmasked data values of another row of the input data in accordance with the mask and an index of the another row;
• merge the R[i] unmasked data values of the row and the N−R[i] data values of the another row to form a combined data vector of N data values;
• and
• compute, by the data normalization circuit comprising a first accumulator and a second accumulator:
• R[i] normalized values based on the R[i] unmasked data values in a first sub-vector of the combined data vector, wherein the data normalization circuit accumulates, in the first accumulator, a first denominator based on the R[i] unmasked data values of the first sub-vector and computes the R[i] normalized values based on the first denominator;
• and
• N−R[i] normalized values based on the N−R[i] data values of a second sub-vector of the combined data vector to generate a combined normalized data vector of N normalized data values, wherein the data normalization circuit accumulates, in the second accumulator, a second denominator based on the N−R[i] unmasked data values of the second sub-vector and computes the N−R[i] normalized values based on the second denominator.