Self-synchronous side-channel attack countermeasure
AssigneeNuvoton Technology Corporation
InventorZiv Hershman
Life of this patent
Estimating the term…
Abstract
An Attack Resilient Computation Circuit (ARCC) in an integrated circuit (IC) includes a first computation stage, a second computation stage, and security circuitry. The first computation stage is configured to process one or more signals so as to produce one or more outputs, the first computation stage having multiple signal propagation paths. The second computation stage is configured to receive and process the outputs of the first computation stage. The security circuitry is configured to generate a synchronization signal indicating that propagation of the signals in the first computation stage has completed, and to inhibit the second processing stage from processing the outputs of the first processing stage for a time interval derived from the synchronization signal.
Claims16
An Attack Resilient Computation Circuit (ARCC) for performing a secure computation in an integrated circuit (IC), the ARCC comprising:
- a first combinatorial logic circuit, configured to perform a first part of the secure computation by processing one or more signals so as to produce one or more outputs, the first combinatorial logic circuit having multiple signal propagation paths;
- a second combinatorial logic circuit, configured to receive and process the outputs of the first combinatorial logic circuit, so as to perform a second part of the secure computation;
- a security gating circuit, which is inserted between the first combinatorial logic circuit and the second combinatorial logic circuit, and is configured to controllably block the outputs of the first combinatorial logic circuit from reaching the second combinatorial logic circuit until propagation of the signals has completed on all the multiple signal propagation paths in the first combinatorial logic circuit;
- and
- security circuitry, configured to mitigate a side-channel attack on the secure computation, by:
- generating a synchronization signal indicating that the propagation of the signals has completed on all the multiple signal propagation paths in the first combinatorial logic circuit;
- and
- controlling the security gating circuit using the synchronization signal to block the second combinatorial logic circuit from receiving and processing the outputs of the first combinatorial logic circuit.
A method for protecting an integrated circuit (IC), the method comprising:
- performing a first part of a secure computation by processing one or more signals in a first combinatorial logic circuit having multiple signal propagation paths, so as to produce one or more outputs;
- receiving and processing the outputs of the first combinatorial logic circuit in a second combinatorial logic circuit, so as to perform a second part of the secure computation;
- and
- using security circuitry, mitigating a side-channel attack on the secure computation, by:
- generating a synchronization signal indicating that propagation of the signals has completed on all the multiple signal propagation paths in the first combinatorial logic circuit;
- and
- controlling a security gating circuit, which is inserted between the first combinatorial logic circuit and the second combinatorial logic circuit, to block the outputs of the first combinatorial logic circuit from reaching the second combinatorial logic circuit, using the synchronization signal, until the propagation of the signals has completed on all the multiple signal propagation paths in the first combinatorial logic circuit.
Dependencies are inferred from the claim text.