Systems and methods for implementing directional operand broadcast and multiply-accumulate execution using a configurable patch mesh in a multi-core processing array of an integrated circuit

A method for operand propagation across overlapping patch regions in a processing array comprising a plurality of processing elements of an integrated circuit, the method comprising:

• implementing an interconnecting processing patch comprising a region of processing elements;
• broadcasting, from an origin processing element of the interconnecting processing patch, operand data across the interconnecting processing patch in a systolic manner;
• implementing a logical processing patch comprising a second region of processing elements, wherein:
• a portion of the interconnecting processing patch overlaps a portion of the logical processing patch to define an interconnecting patch mesh, and
• the interconnecting processing patch and the logical processing patch share a common subset of processing elements;
• and
• propagating operand data from the origin processing element of the interconnecting processing patch to the common subset of processing elements in the interconnecting patch mesh.

A method comprising:

• implementing a first patch comprising a region of processing elements;
• broadcasting, from an origin processing element of the first patch, operand data across the first patch in a systolic manner;
• implementing a second patch comprising a second region of processing elements, wherein:
• a portion of the first patch overlaps a portion of the second patch to define a patch mesh, and
• the first patch and the second patch share a common subset of processing elements;
• and
• propagating operand data from the origin processing element of the first patch to the common subset of processing elements in the patch mesh.

A system comprising:

• a processing array comprising a plurality of processing elements formed within an integrated circuit;
• a configuration controller operable to define:
• an interconnecting processing patch comprising a first rectilinear region encompassing a subset of the plurality of processing elements, the interconnecting processing patch including an origin processing element configured to broadcast operand data to remaining processing elements of the interconnecting processing patch in a time-staggered, directionally constrained wavefront pattern;
• and
• a logical processing patch comprising a second rectilinear region encompassing a second subset of the plurality of processing elements;
• wherein a portion of the interconnecting processing patch overlaps a portion of the logical processing patch to define an interconnecting patch mesh comprising a common set of processing elements shared by the interconnecting processing patch and the logical processing patch;
• and
• wherein the processing elements of the interconnecting patch mesh are configured to receive the operand data from the origin processing element and perform accumulation or operand handoff to surrounding processing elements of the logical processing patch.