Address length selection for inter-integrated circuit (I2C) communications
AssigneeQUALCOMM Incorporated
InventorsSaravana Babu C, Aasaithambi Durairajan, Amit Gil, Sang Tran
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AssigneeQUALCOMM Incorporated
InventorsSaravana Babu C, Aasaithambi Durairajan, Amit Gil, Sang Tran
Estimating the term…
A device includes a processing system configured to receive, via an inter-integrated circuit (I2C) bus, one or more scan acknowledgement messages respectively associated with one or more secondary devices and to send, via the I2C bus, one or more address assignment messages to the one or more secondary devices. The one or more address assignment messages respectively include one or more logical addresses that are associated with the one or more secondary devices. The processing system is further configured to communicate, via the I2C bus, a data message with at least one secondary device of the one or more secondary devices. The data message includes an address field including a logical address indicating that the data message is associated with the at least one secondary device. A length of the address field is based on a quantity of the one or more scan acknowledgement messages.
A device comprising:
A method of operation of a device, the method comprising:
A non-transitory computer-readable medium storing instructions executable by one or more processors of a device to initiate, control, or perform operations, the operations comprising:
Dependencies are inferred from the claim text.