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US 12,596,664 B2Granted
Data processing method and electronic device using dma
AssigneeRebellions Inc.
InventorsBoeui Hong, Jaedon Lee, Jiun Yu, Hyebin Jeong, Sangjun Nam, Hongyun Kim
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Abstract
A data processing method using a DMA, the method comprising: deriving a waiting time of a waiting time of a first DMA operation for a first computation task and a waiting time of a second DMA operation for a second computation task, deriving a MO value of the first DMA operation and a MO value of the second DMA operation based on the waiting time of the first DMA operation and the waiting time of the second DMA operation, and performing the first DMA operation based on the MO value of the first DMA operation, and performing the second DMA operation based on the MO value of the second DMA operation.
Claims20
A data processing method using a direct memory access (DMA), the method comprising:
- deriving a waiting time of a first DMA operation for a first computation task and a waiting time of a second DMA operation for a second computation task;
- deriving a Multiple Outstanding (MO) value of the first DMA operation and a MO value of the second DMA operation based on the waiting time of the first DMA operation and the waiting time of the second DMA operation, the MO value of a DMA operation representing a number of outstanding data transactions associated with the DMA operation for a plurality of computation tasks to be executed including the first computation task and the second computation task, wherein a ratio of the MO value of the first DMA operation to the MO value of the second DMA operation is adjusted based on a comparison of the waiting time of the first DMA operation and the waiting time of the second DMA operation to allocate more shared DMA bandwidth over a shared memory bus to the first DMA operation or the second DMA operation having the smaller waiting time;
- and
- performing the first DMA operation based on the MO value of the first DMA operation, and performing the second DMA operation based on the MO value of the second DMA operation,
- wherein the waiting time of the first DMA operation is derived as a sum of predicted execution times of computation tasks performed before the first computation task among waiting computation tasks, and
- wherein the waiting time of the second DMA operation is derived as a sum of predicted execution times of computation tasks performed before the second computation task among the waiting computation tasks.
3 more elements
An electronic device, comprising:
- a command processor (CP) that operates firmware for a direct memory access (DMA) operation;
- a first DMA device performing a first DMA operation between a first memory and a specific memory;
- and
- a second DMA device performing a second DMA operation between a second memory and the specific memory,
- wherein the CP derives a waiting time of the first DMA operation for a first computation task and a waiting time of the second DMA operation for a second computation task, derives a Multiple Outstanding (MO) value of the first DMA operation and a MO value of the second DMA operation based on the waiting time of the first DMA operation and the waiting time of the second DMA operation, the MO value of a DMA operation representing a number of outstanding data transactions associated with the DMA operation for a plurality of computation tasks to be executed including the first computation task and the second computation task, wherein a ratio of the MO value of the first DMA operation to the MO value of the second DMA operation is adjusted based on a comparison of the waiting time of the first DMA operation and the waiting time of the second DMA operation to allocate more shared DMA bandwidth over a shared memory bus to the first DMA operation or the second DMA operation having the smaller waiting time,
- wherein the first DMA device performs the first DMA operation based on the MO value of the first DMA operation,
- wherein the second DMA device performs the second DMA operation based on the MO value of the second DMA operation,
- wherein the waiting time of the first DMA operation is derived as a sum of predicted execution times of computation tasks performed before the first computation task among waiting computation tasks, and
- wherein the waiting time of the second DMA operation is derived as a sum of predicted execution times of computation tasks performed before the second computation task among the waiting computation tasks.
6 more elements
Dependencies are inferred from the claim text.