User controlled allocation of a specific cache line at time of access
AssigneeInternational Business Machines Corporation
InventorScot Rider
Life of this patent
Estimating the term…
Abstract
Systems and techniques for controlling allocation of a cache line when performing a memory access request are described. An example technique includes receiving a memory access request from a user interface. The memory access request includes an indication of whether a cache line associated with the memory access request is to be allocated into a lower level cache within a computing system. The cache line is written into a line buffer within a line engine in the computing system in response to receiving the memory access request. The cache line is moved from the line buffer to an upper level cache in the computing system, without involving the lower level cache, when the memory access request indicates the cache line is not to be allocated into the lower level cache.
Claims20
A computer-implemented method comprising:
- receiving, at runtime via an external user interface, a user-initiated memory access request, wherein the user-initiated memory access request comprises an indication of whether a cache line associated with the user-initiated memory access request is to be allocated into a lower level cache within a computing system;
- writing the cache line into a line buffer within a line engine in the computing system in response to receiving the user-initiated memory access request;
- and
- moving the cache line from the line buffer within the line engine to an upper level cache in the computing system via a data path that excludes the lower level cache, in response to the user-initiated memory access request indicating the cache line is not to be allocated into the lower level cache, wherein the line engine is external to the lower level cache and the upper level cache in the computing system.
A system comprising:
- a plurality of line engines, each line engine of the plurality of line engines comprising a respective line buffer;
- a lower level cache external to the plurality of line engines;
- and
- an upper level cache external to the plurality of line engines, wherein at least a first line engine of the plurality of line engines comprises logic configured to perform an operation comprising:
- receiving, at runtime via an external user interface, a user-initiated memory access request, wherein the user-initiated memory access request comprises an indication of whether a cache line associated with the user-initiated memory access request is to be allocated into the lower level cache;
- writing the cache line into the line buffer within the first line engine in response to receiving the user-initiated memory access request;
- and
- moving the cache line from the line buffer within the first line engine to the upper level cache via a data path that excludes the lower level cache, in response to the user-initiated memory access request indicating the cache line is not to be allocated into the lower level cache.
A computer-readable storage medium having computer-readable program code embodied therewith, the computer-readable program code executable by one or more computer processors to perform an operation comprising:
- receiving, at runtime via an external user interface, a user-initiated memory access request, wherein the user-initiated memory access request comprises an indication of whether a cache line associated with the user-initiated memory access request is to be allocated into a lower level cache within a computing system;
- writing the cache line into a line buffer within a line engine in the computing system in response to receiving the user-initiated memory access request;
- and
- moving the cache line from the line buffer within the line engine to an upper level cache in the computing system via a data path that excludes the lower level cache, in response to the user-initiated memory access request indicating the cache line is not to be allocated into the lower level cache, wherein the line engine is external to the lower level cache and the upper level cache in the computing system.
Dependencies are inferred from the claim text.