Preemptive flushing of processing-in-memory data structures
AssigneeAdvanced Micro Devices, Inc.
InventorsDavid Andrew Werner, Travis Henry Boraten, Michael Warren Boyer
Life of this patent
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Abstract
Preemptive flushing of data involved in executing a processing-in-memory command, from a cache system to main memory that is accessible by a processing-in-memory component, is described. In one example, a system includes an asynchronous flush controller that receives an indication of a subsequent processing-in-memory command to be executed as part of performing a computational task. While earlier commands of the computational task are executed, the asynchronous flush controller evicts or invalidates data elements involved in executing the subsequent processing-in-memory command from the cache system, such that the processing-in-memory command can proceed without stalling.
Claims20
A system comprising:
- a cache system including a plurality of cache levels;
- and
- a cache controller configured to:
- identify that a processing-in-memory command involves a plurality of data elements stored at an address range in the cache system;
- and
- responsive to the address range satisfying a threshold size, evict a portion of the plurality of data elements from the cache system prior to issuance of the processing-in-memory command, the evicted portion of the plurality of data elements excluding some of the plurality of data elements.
A device comprising:
- a cache controller configured to:
- receive an indication that a processing-in-memory command to be subsequently executed involves a plurality of data elements;
- perform a cache directory lookup to determine whether the plurality of data elements are stored at an address range in a cache system;
- and
- responsive to the address range satisfying a threshold size, evict a portion of the plurality of data elements from the cache system prior to issuance of the processing-in-memory command, the evicted portion of the plurality of data elements excluding some of the plurality of data elements.
A method comprising:
- executing, by a core of a processing unit, a plurality of commands as part of performing a computational task;
- identifying that the plurality of commands include a processing-in-memory instruction that accesses a plurality of data elements stored at an address range in a cache system during performance of the computational task;
- identifying that the address range satisfies a threshold size;
- responsive to the address range satisfying the threshold size, and while the core of the processing unit is executing a portion of the plurality of commands that occur prior to the processing-in-memory instruction, evicting a portion of the plurality of data elements from the cache system, the portion of the plurality of data elements excluding at least one of the plurality of data elements;
- and
- transmitting, by the core of the processing unit, the processing-in-memory instruction to a processing-in-memory component after the portion of the plurality of data elements is evicted from the cache system.
Dependencies are inferred from the claim text.