Cache management using shared cache line storage

A computer program product embodied in a non-transitory computer readable medium for cache management, the computer program product comprising code which causes one or more processors to generate semiconductor logic for:

• accessing a plurality of processor cores, wherein the plurality of processor cores comprises a coherency domain, and wherein two or more processor cores within the plurality of processor cores generate read operations for a common memory structure coupled to the plurality of processor cores, wherein the memory accesses are performed over a network-on-chip, wherein non-cacheable memory accesses are targeted to memory mapped input and output (I/O) locations within the common memory structure, wherein the non-cacheable memory accesses are aligned to a cache line boundary;
• managing coherency for the coherency domain using a compute coherency block (CCB), wherein the CCB includes a memory queue for storing cache lines determined by the CCB;
• generating snoop requests, by the CCB, wherein the snoop requests correspond to entries in the memory queue;
• and
• transferring cache lines between the compute coherency block and a bus interface unit, wherein the transferring is controlled by the memory queue, wherein the transferring occurs from the CCB to the bus interface unit when the cache line is an evicted cache line;
• and
• committing the evicted cache line to the common memory structure.

An apparatus for cache management comprising:

• a plurality of processor cores, wherein the plurality of processor cores comprises a coherency domain, and wherein two or more processor cores within the plurality of processor cores generate memory accesses for a common memory structure coupled to the plurality of processor cores, wherein the memory accesses are performed over a network-on-chip, wherein non-cacheable memory accesses are targeted to memory mapped input and output (I/O) locations within the common memory structure, wherein the non-cacheable memory accesses are aligned to a cache line boundary;
• a compute coherency block (CCB) for managing coherency within the coherency domain, wherein the CCB is coupled to the plurality of processor cores and includes a memory queue for storing cache lines determined by the CCB;
• a bus interface unit, wherein the bus interface unit is coupled to the CCB and implements memory accesses;
• and wherein
• the CCB generates snoop requests, wherein the snoop requests correspond to entries in the memory queue;
• and
• cache lines are transferred between the compute coherency block and the bus interface unit, under control of the memory queue, wherein transferring occurs from the CCB to the bus interface unit when the cache line is an evicted cache line;
• and
• the evicted cache line is committed to the common memory structure.