Memory management among multiple erase blocks coupled to a same string
AssigneeMicron Technology, Inc.
InventorsKishore K. Muchherla, Hong Lu, Mark Ish, Akira Goda
Life of this patent
Estimating the term…
Loading patent…
AssigneeMicron Technology, Inc.
InventorsKishore K. Muchherla, Hong Lu, Mark Ish, Akira Goda
Estimating the term…
An apparatus can comprise a memory array comprising a plurality of erase blocks and a plurality of strings of memory cells. Each string of the plurality of strings can comprise: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller coupled to the memory array can be configured to: receive a write command corresponding to data to be written to the memory array; determine a temperature classification for the data to which the write command corresponds; and, based on the determined temperature classification for the data, route the data to a first write cursor or to one of a number of different write cursors.
A method, comprising:
An apparatus, comprising:
An apparatus, comprising:
Dependencies are inferred from the claim text.