Techniques for logical-to-physical information compression

An apparatus, comprising:

• one or more controllers associated with a memory device, wherein the one or more controllers are configured to cause the apparatus to:
• receive, by a memory system and from a host system, a read command comprising a logical address;
• access one or more candidate entries in a mapping between a plurality of logical addresses and a plurality of physical addresses based at least in part on receiving the read command to identify a physical address associated with the logical address, the mapping comprising a plurality of entries each configured to store an indication of a sequence of consecutive physical addresses of the plurality of physical addresses, the indication comprising a starting physical address of the sequence associated with a starting logical address and an index from a same reference entry of the plurality of entries of the mapping, the index for each entry based at least in part on the starting logical address for the entry and a reference logical address of the same reference entry of the plurality of entries;
• and
• transmit data stored at the physical address to the host system.

A non-transitory computer-readable medium storing code comprising instructions which, when executed by a processor of an electronic device, cause the electronic device to:

• identify a first mapping between a plurality of logical addresses and a plurality of physical addresses stored in a region of a cache of a memory system;
• generate a second mapping between the plurality of logical addresses and the plurality of physical addresses based at least in part on the first mapping, the second mapping comprising a plurality of entries each configured to store an indication of a sequence of consecutive physical addresses of the plurality of physical addresses, the indication comprising a starting physical address of the sequence associated with a starting logical address and an index from a same reference entry of the plurality of entries of the second mapping, the index for each entry based at least in part on the starting logical address for the entry and a reference logical address of the same reference entry of the plurality of entries;
• and
• store the second mapping to the region.