High-speed debug port trace circuit

An integrated circuit including a high-speed debug port trace (HSDPT) circuit, wherein the HSDPT circuit comprises:

• a plurality of input receiver circuits each configured to receive a stream of trace data, wherein the plurality of input receiver circuits receive streams of trace data from a plurality of compute circuits of different compute circuit types, wherein the plurality of compute circuits are within the integrated circuit;
• wherein the input receiver circuits are configured to drop one or more packets of trace data within respective ones of the streams of trace data in response to detecting back pressure or a failed check for expected packet length;
• a stream selector circuit configured to perform multiple stages of arbitration among the plurality of streams of trace data to generate output trace data;
• wherein the stream selector circuit includes a first stage arbitration circuit configured to arbitrate only among trace data from a data processing array and a different first stage arbitration circuit configured to arbitrate only among trace data from programmable logic;
• wherein the stream selector circuit includes a second stage arbitration circuit configured to;
• insert compute circuit type identifiers within packets of the trace data based on a particular first stage arbitration circuit from which the trace data is received, wherein each compute circuit type identifier specifies a compute circuit type that originated each portion of trace data;
• and
• an output transmitter circuit configured to output the trace data, wherein the output transmitter circuit includes a compressor circuit configured to compress the trace data prior to storage of the trace data within a first-in-first-out memory;
• wherein the HSDPT circuit further comprises a controller configured to track packets of trace data dropped from the streams of trace data and a memory coupled to the controller, wherein the controller is configured to store packet loss information within the memory, wherein the packet loss information indicates an amount of trace data that was dropped;
• wherein the HSDPT is compiled within a circuit design for implementation the integrated circuit.