US 12,596,611 B2Granted

Memory system and memory management method thereof

AssigneeNuvoton Technology Corporation

InventorPao-Chen Ko

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Abstract

A memory system including a memory; an encoding management circuit; and a memory access instruction decoding unit is provided. The memory access instruction decoding unit is configured to receive an instruction from a bus, identify a bad block in the memory, determine whether the instruction indicates access to the bad block. When the instruction indicates writing data to the bad block, the memory access instruction decoding unit outputs an address of the bad block and the data to the encoding management circuit to trigger the encoding management circuit to update the encoding management circuit. When the instruction indicates reading the bad block, the memory access instruction decoding unit outputs the address to and trigger the encoding management circuit to output simulation data of the bad block, wherein the encoding management circuit obtains the simulation data based on the address.

Claims9

Dependent claims

A memory system, comprising:

a memory;
an encoding management circuit;
and
a memory access instruction decoding unit, signally connected to the memory and the encoding management circuit, and configured to:
receive an instruction from a bus;
identify a bad block in the memory;
determine whether the instruction indicates accessing to the bad block;
when the instruction indicates writing data to the bad block, output an address of the bad block and the data to the encoding management circuit to trigger the encoding management circuit to update the encoding management circuit;
and
when the instruction indicates reading the bad block, output the address of the bad block to the encoding management circuit to trigger the encoding management circuit to output simulation data of the bad block,
wherein the encoding management circuit obtains the simulation data of the bad block based on the address of the bad block, and
wherein the memory system further comprising a multiplexer signally connected to the memory, the encoding management circuit, and the memory access instruction decoding unit, wherein when the instruction indicates reading the bad block, the multiplexer receives the simulation data of the bad block from the encoding management circuit and outputs the simulation data of the bad block to the bus, and when the instruction indicates reading a normal block in the memory, the multiplexer receives actual data stored in the normal block from the memory and outputs the actual data to the bus.

9 more elements

A memory management method, comprising:

receiving an instruction from a bus, by a memory access instruction decoding unit;
identifying a bad block in a memory, by the memory access instruction decoding unit;
determining whether the instruction indicates accessing to the bad block, by the memory access instruction decoding unit;
when the instruction indicates writing data to the bad block, outputting an address of the bad block and the data to an encoding management circuit, by the memory access instruction decoding unit, and updating the encoding management;
and
when the instruction indicates reading the bad block, outputting the address of the bad block to the encoding management circuit, by the memory access instruction decoding unit, obtaining simulation data of the bad block based on the address of the bad block and outputting the simulation data of the bad block, by the encoding management circuit.

3 more elements

Dependencies are inferred from the claim text.