# US 12,596,610 B2 · Parity data in dynamic random access memory (DRAM) > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,596,610 B2 - Document ID: US12596610B2 - Status: Granted - Kind: B2 - Application number: 18/800,272 - Filed: 2024-08-12 - Published: 2024-12-05 - Granted: 2026-04-07 - Earliest claimed: 2020-12-22 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Sai Krishna Mylavarapu; Todd A. Marquart - Web page: https://patentgrep.com/patent/US12596610B2 ## CPC - G06F 11/1004: {to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00)} - G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature} - G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)} - G11C 11/005: {comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells} - G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits - G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 2029/0409: {Online test} - G11C 2029/0411: {Online error correction} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Methods, devices, and systems related to storing parity data in dynamic random access memory (DRAM) are described. In an example, a method can include generating, at a controller, parity data based on user data queued for writing to a non-volatile memory device, receiving the parity data at a DRAM device from the controller and writing the parity data to the DRAM device, receiving the user data at a non-volatile memory device from the controller and writing the user data to the non-volatile memory device, reading the user data from the non-volatile memory device via the controller, and receiving the parity data at the controller from the DRAM device. ## Claims ### Claim 1 A method, comprising: receiving user data from a non-volatile memory device at a controller of a dual in-line memory module (DIMM); receiving parity data corresponding to the user data from a dynamic random access memory (DRAM) device at the controller; and reconstructing the user data at the controller using the parity data. ### Claim 2 (depends on 1) The method of claim 1, further comprising regenerating the parity data in response to powering off and powering on the DRAM device. ### Claim 3 (depends on 1) The method of claim 1, further comprising receiving the parity data in response to a read failure. ### Claim 4 (depends on 3) The method of claim 3, further comprising reconstructing the user data in response to the read failure. ### Claim 5 (depends on 4) The method of claim 4, wherein the read failure is due to corrupted memory in the non-volatile memory device. ### Claim 6 (depends on 1) The method of claim 1, further comprising reading the user data and reconstructing the user data in one clock cycle. ### Claim 7 (depends on 1) The method of claim 1, further comprising generating the parity data at the controller by performing an error correction code (ECC) operation on the user data. ### Claim 8 (depends on 1) The method of claim 1, further comprising performing a RAID operation on the user data to generate the parity data at the controller. ### Claim 9 A dual in-line memory module (DIMM), comprising: a dynamic random access memory (DRAM) device; a non-volatile memory device coupled to the DRAM device, wherein the non-volatile memory device is configured to store user data; and a controller coupled to the DRAM device and the non-volatile memory device, wherein the controller is configured to: receive the user data from the non-volatile memory device; and perform an error correction code (ECC) operation on the user data to regenerate parity data. ### Claim 10 (depends on 9) The DIMM of claim 9, wherein the controller is configured to perform the ECC operation on the user data to regenerate the parity data in response to powering on the DRAM device. ### Claim 11 (depends on 9) The DIMM of claim 9, wherein the controller comprises an error correction code (ECC) module configured to perform the ECC operation. ### Claim 12 (depends on 9) The DIMM of claim 9, wherein the ECC operation is an XOR operation. ### Claim 13 (depends on 9) The DIMM of claim 9, wherein the controller is configured to perform the ECC operation in one clock cycle. ### Claim 14 (depends on 9) The DIMM of claim 9, wherein the controller is configured to rewrite the parity data to the DRAM device in response to powering on the DRAM device. ### Claim 15 A dual in-line memory module (DIMM), comprising: a controller configured to generate parity data based on user data; a dynamic random access memory (DRAM) device configured to store the parity data; and a non-volatile memory device configured to store the parity data prior to powering off the DRAM device; and wherein the controller is configured to rewrite the parity data to the DRAM device in response to powering on the DRAM device. ### Claim 16 (depends on 15) The DIMM of claim 15, wherein the non-volatile memory device is configured to store the user data. ### Claim 17 (depends on 15) The DIMM of claim 15, wherein the non-volatile memory device is a 3D Cross-point device. ### Claim 18 (depends on 15) The DIMM of claim 15, wherein the controller is configured to generate the parity data based on the user data in response to receiving a write command. ### Claim 19 (depends on 18) The DIMM of claim 18, wherein the write command includes the user data. ### Claim 20 (depends on 15) The DIMM of claim 15, wherein the user data is queued for writing to the non-volatile memory device.