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US 12,596,609 B2Granted
Error detection in communications over serial peripheral interfaces
AssigneeMicron Technology, Inc.
InventorMinjian Wu
Life of this patent
Estimating the term…
Abstract
A memory device and a host system configured to transmit, using serial peripheral interfaces, an item (e.g., a command, an address, or a data item) followed by a cyclic redundancy check value of the item using operations same as transmission of one or more bits of the item. If the received cyclic redundancy check value does not match with the cyclic redundancy check value computed from the received item, an interrupt signal can be transmitted via a control line of a serial peripheral interface bus to request re-transmission of the item. When the host system detects a transmission error in receiving data from the memory device the serial peripheral interface bus, the host system can terminate the read command and re-transmit the read command.
Claims17
A method, comprising:
- communicating, between a memory device and a host system, a clock signal over a first control line of a serial peripheral interface bus connected between the memory device and the host system;
- communicating, between the memory device and the host system, an item over a plurality of data lines of the serial peripheral interface bus during a first time period of one or more clock cycles identified using the clock signal;
- computing a cyclic redundancy check value of the item;
- communicating, between the memory device and the host system, the cyclic redundancy check value over the plurality of data lines during a second time period of one or more clock cycles identified using the clock signal;
- determining whether a communication error has occurred in transmission of the item and the cyclic redundancy check value over the serial peripheral interface bus;
- and
- setting an error bit in a status register in the memory device in response to a determination that a communication error has occurred in transmission of the item and the cyclic redundancy check value over the serial peripheral interface bus;
- wherein the determining of whether a communication error has occurred is based on comparing the cyclic redundancy check value received via the serial peripheral interface bus and a cyclic redundancy check value computed from the item received via the serial peripheral interface bus;
- wherein the second time period follows the first time period without a time gap longer than a quarter of a clock cycle.
6 more elements
A memory device, comprising:
- memory cells;
- a serial peripheral interface configured to:
- receive a clock signal over a first control line of a serial peripheral interface bus connected between the memory device and a host system;
- receive a command to access the memory cells over a plurality of data lines of the serial peripheral interface bus during a first time period identified using the clock signal;
- and
- receive a first cyclic redundancy check value over the plurality of data lines during a second time period identified using the clock signal;
- and
- a cyclic redundancy check module configured to compute a second cyclic redundancy check value from the command received in the serial peripheral interface and compare the first cyclic redundancy check value and the second cyclic redundancy check value to detect a communication error in transmission of the command;
- wherein the second time period is configured to follow the first time period without a time gap longer than a quarter of a clock cycle;
- and the serial peripheral interface is further configured to receive an address for the command to access the memory cells over the plurality of data lines of the serial peripheral interface bus during a third time period identified using the clock signal.
7 more elements
A host system, comprising:
- a cyclic redundancy check module configured to compute a first cyclic redundancy check value of a command, and a third cyclic redundancy check value of an address;
- and
- a serial peripheral interface configured to:
- transmit a clock signal over a first control line of a serial peripheral interface bus connected between the host system and a memory device;
- transmit the command to access the memory device over a plurality of data lines of the serial peripheral interface bus during a first time period identified using the clock signal;
- transmit the first cyclic redundancy check value of the command over the plurality of data lines during a second time period identified using the clock signal, wherein the second time period is configured to follow the first time period without a time gap longer than a quarter of a clock cycle;
- transmit the address for the command over the plurality of data lines of the serial peripheral interface bus during a third time period identified using the clock signal;
- and
- transmit the third cyclic redundancy check value over the plurality of data lines during a fourth time period identified using the clock signal, the fourth time period configured to follow the third time period without the time gap;
- wherein the memory device is configured to compute a second cyclic redundancy check value of the command and a fourth cyclic redundancy check value of the address to detect an error in transmission of the command and the address;
- and in response to the error, the memory device is configured to assert an interrupt signal in a second control line of the serial peripheral interface bus.
8 more elements
Dependencies are inferred from the claim text.