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US 12,596,608 B2Granted
Row mapping in a memory controller
AssigneeMicron Technology, Inc.
InventorsAntonino Capri, John Namkung
Life of this patent
Estimating the term…
Abstract
A row can be mapped to a spare row in memory. The mapping can include stopping the scheduler from issuing commands to the first bank. Responsive to stopping the scheduler from issuing commands to the first bank, the logic can map a particular row of the first bank to the spare row. The mapping can include allowing the scheduler to schedule commands for the second bank concurrently with the mapping of the particular row to the spare row.
Claims20
An apparatus comprising:
- a memory device comprising:
- a first bank of memory cells comprising a plurality of rows of memory cells and a spare row of memory cells;
- a second bank of memory cells;
- a controller coupled to the memory device and comprising:
- memory;
- a scheduler;
- and
- logic coupled to the scheduler and configured to:
- receive a command from a host to map a particular row of the first bank of memory cells to the spare row of the first bank;
- responsive to receipt of the command, copy data from the particular row to the memory;
- prevent the refresh circuitry of the controller from refreshing the first bank responsive to copying the data to the memory;
- prevent the scheduler from issuing commands to the first bank, responsive to copying the data to the memory;
- responsive to preventing the scheduler from issuing commands to the first bank and preventing the refresh circuitry from refreshing the first bank map the particular row of the first bank to the spare row;
- and
- allow the scheduler to schedule commands for the second bank concurrently with the mapping of the particular row to the spare row.
12 more elements
A method, comprising:
- receiving a command from a host at a controller of a memory sub-system, to map a failing row of a first bank of a memory device of the memory sub-system to a spare row of the first bank;
- responsive to receipt of the command, copying, utilizing logic of the controller, data from the failing row to memory of the controller;
- responsive to copying the data to the memory of the controller, stopping, utilizing the logic, refresh circuitry of the controller from refreshing the first bank;
- responsive to stopping the refresh circuitry from refreshing the first bank, mapping, utilizing the logic, the failing row to the spare row;
- refreshing a second bank of the memory device concurrently with the mapping of the failing row to the spare row;
- and
- responsive to mapping the failing row to the spare row, copying the data from the memory to the spare row.
4 more elements
An apparatus comprising:
- a scheduler;
- refresh circuitry;
- memory;
- logic coupled to the scheduler, the refresh circuitry, and the memory and configured to:
- monitor a plurality of registers that store bits that identify a first failing row of a first bank and a second failing row of a second bank;
- responsive to monitoring the plurality of registers, copy first data from the first failing row to the memory;
- responsive to monitoring the plurality of registers, copy second data from the second failing row to the memory;
- responsive to copying the first data to the memory and the second data to the memory, stop the scheduler from issuing commands to the first bank and to the second bank;
- responsive to copying the first data to the memory and the second data to the memory, stop the refresh circuitry from refreshing the first bank and the second bank;
- responsive to stopping the scheduler from issuing commands to the first bank and to stopping the refresh circuitry from refreshing the first bank and the second bank, map the first failing row to a first spare row of the first bank and the second failing row to a second spare row of the second bank;
- allow the scheduler to schedule commands for other banks concurrently with the mapping of the first failing row to the first spare row;
- allow the refresh circuitry to refresh the other banks concurrently with the mapping of the second failing row to the second spare row;
- responsive to mapping the first failing row to the first spare row, copy the first data from the memory to the first spare row;
- and
- responsive to mapping the second failing row to the second spare row, copy the second data from the memory to the second spare row.
12 more elements
Dependencies are inferred from the claim text.