Verifying processing logic of a graphics processing unit
AssigneeImagination Technologies Limited
InventorDonald Scorgie
Life of this patent
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Abstract
A method of verifying processing logic of a graphics processing unit receives a test task including a predefined set of instructions for execution on the graphics processing unit, the predefined set of instructions being configured to perform a predetermined set of operations on the graphics processing unit when executed for predefined input data. In a test phase, the test task is processed by executing the predefined set of instructions for the predefined input data first and second times at the graphics processing unit so as to, respectively, generate first and second outputs. A fault signal is raised if the first and second outputs do not match.
Claims20
A method of verifying processing logic of a graphics processing unit, the method comprising a test phase and a non-test phase,
- the test phase comprising:
- receiving a test task at the graphics processing unit;
- processing the test task by executing a predefined set of instructions for predefined input data first and second times at the graphics processing unit so as to respectively generate first and second test outputs;
- and
- raising a fault signal if the first and second test outputs do not match;
- and
- the non-test phase comprising:
- receiving one or more non-test tasks for processing at the graphics processing unit;
- and
- in response to determining that a number of fault signals raised in the test phase exceeds a threshold:
- processing a non-test task first and second times at the graphics processing unit so as to, respectively, generate first and second non-test outputs;
- and
- raising a further fault signal if the first and second non-test outputs do not match.
A graphics processing unit configured to receive a test task and one or more non-test tasks for processing at the graphics processing unit, the graphics processing unit comprising:
- processing logic being configured to, in a test phase, process the test task by executing a predefined set of instructions for predefined input data first and second times at the graphics processing unit so as to, respectively, generate first and second test outputs;
- a check unit being configured to, in the test phase, raise a fault signal if the first and second test outputs do not match;
- the processing logic further configured to, if a number of fault signals raised in the test phase exceeds a threshold, in a non-test phase, process a non-test task first and second times at the graphics processing unit so as to, respectively, generate first and second non-test outputs;
- and
- the check unit further configured to, in the non-test phase, raise a further fault signal if the first and second non-test outputs do not match.
A non-transitory computer readable storage medium having stored thereon computer readable instructions that, when executed at a computer system, cause the computer system to perform a method of verifying processing logic of a graphics processing unit, the method comprising a test phase and a non-test phase,
- the test phase comprising:
- receiving a test task at the graphics processing unit;
- processing the test task by executing a predefined set of instructions for predefined input data first and second times at the graphics processing unit so as to, respectively, generate first and second test outputs;
- and
- raising a fault signal if the first and second test outputs do not match;
- and the non-test phase comprising:
- receiving one or more non-test tasks for processing at the graphics processing unit;
- and
- in response to determining that a number of fault signals raised in the test phase exceeds a threshold:
- processing a non-test task first and second times at the graphics processing unit so as to, respectively, generate first and second non-test outputs;
- and
- raising a further fault signal if the first and second non-test outputs do not match.
Dependencies are inferred from the claim text.