Subscription to sync zones
AssigneeGraphcore Limited
InventorsStephen Felix, Richard Osborne
Life of this patent
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Abstract
A set of configurable sync groupings (which may be referred to as sync zones) are defined. Any of the processors may belong to any of the sync zones. Each of the processor comprises a register indicating to which of the sync zones it belongs. If a processor does not belong to a sync zone, it continually asserts a sync request for that sync zone to the sync controller. If a processor does belong to a sync zone, it will only assert its sync request for that sync zone upon arriving at a synchronisation point for that sync zone indicated in its compiled code set.
Claims25
A data processing device comprising:
- a plurality of processors;
- and
- a sync controller comprising circuitry configured to receive requests from the plurality of processors to participate in synchronisations and, in response to receiving the requests, return acknowledgments to the processors,
- wherein each of the plurality of processors comprises:
- an execution unit configured to execute a set of computer readable instructions held in memory of the respective processor;
- and
- a register storing, for each of a set of configurable sync groups, an indication as to whether or not the respective processor belongs to the respective configurable sync group,
- wherein for a first processor of the plurality of processors:
- a first indication for a first configurable sync group of the set of configurable sync groups indicates that the first processor of the plurality of processors does not belong to the first configurable sync group of the set of configurable sync groups;
- and
- a second indication for a second configurable sync group of the se of configurable sync groups indicates that the first processor of the plurality of processors does belong to the second configurable sync group of the set of configurable sync groups,
- wherein the first processor of the plurality of processors comprises circuitry configured to, in response to the first indication for the first configurable sync group of the set of configurable sync groups indicating that the first processor of the plurality of processors does not belong to the first configurable sync group of the set of configurable sync groups, assert a first request to the sync controller to participate in a synchronisation for the first configurable sync group of the set of configurable sync groups,
- wherein the circuitry of the first processor of the plurality of processors is configured to, in response to the execution unit of the first processor of the plurality of processors reaching a synchronisation point for the second configurable sync group of the set of configurable sync groups indicated in the set of computer readable instructions for the first processor of the plurality of processors, assert a second request to the sync controller to participate in a synchronisation for the second configurable sync group of the set of configurable sync groups,
- further comprising aggregation circuitry configured to:
- in response to each of the plurality of processors providing the first request to participate in the synchronisation for the first configurable sync group, provide a first aggregate sync request to the sync controller;
- and
- in response to each of the plurality of processors providing the second request to participate in the synchronisation for the second configurable sync group, provide a second aggregate sync request to the sync controller,
- wherein the circuitry of the sync controller is configured to return acknowledgments to the plurality of processors in response to each of the first aggregate sync request and the second aggregate sync request.
A method implemented in a data processing device comprising a plurality of processors, the method comprising:
- storing a first indication in a memory of a first processor of the plurality of processors, the first indication indicating that the first processor does not belong to a first configurable sync group;
- and
- storing a second indication in the memory of the first processor, the second indication indicating that the first processor does belong to a second configurable sync group,
- wherein the method comprises:
- at a sync controller, receiving requests from the plurality of processors to participate in synchronisations and, in response to receiving the requests, returning acknowledgments to the plurality of processors;
- at the first processor, in response to the first indication, asserting a first request to the sync controller to participate in a synchronisation for the first configurable sync group;
- and
- in response to an execution unit of the first processor reaching a synchronisation point for the second configurable sync group, asserting a second request to the sync controller to participate in a synchronisation for the second configurable sync group;
- a second processor of the plurality of processors issuing a further request to participate in the synchronisation for the first configurable sync group upon reaching a first barrier synchronisation enforced between a subset of the plurality of processors, the subset of the plurality of processors belonging to the first configurable sync group;
- and
- the first processor proceeding with computation or data exchange without waiting at the first barrier synchronisation, whilst the second processor is paused waiting at the first barrier synchronisation.
An integrated circuit comprising:
- a plurality of processors;
- and
- a sync controller comprising circuitry configured to coordinate synchronisations among the processors,
- wherein a first processor of the plurality of processors comprises:
- an execution unit configured to execute a set of computer readable instructions held in memory of the first processor;
- and
- a register storing a first indication indicating that the first processor does not belong to a first configurable sync group and a second indication indicating that the first processor does belong to a second configurable sync group,
- wherein the first processor of the plurality of processors comprises circuitry configured to, in response to the first indication, assert a first request to the sync controller to participate in a synchronisation for the first configurable sync group,
- wherein the circuitry of the first processor of the plurality of processors is configured to, in response to the first processor reaching a synchronisation point for the second configurable sync group, assert a second request to the sync controller to participate in a synchronisation for the second configurable sync group;
- wherein the circuitry of the first processor of the plurality of processors is configured to:
- receive from the execution unit of the first processor of the plurality of processors, a control signal indicating that the execution unit has reached the synchronisation point for the second configurable sync group;
- and
- convert the control signal to the second request to participate in the synchronisation for the second configurable sync group.
Dependencies are inferred from the claim text.