Integrated circuit and method of forming the same

A memory cell array, comprising:

• a first bank of memory cells comprising a first memory cell;
• a second bank of memory cells adjacent to the first bank of memory cells, the second bank of memory cells comprising a second memory cell;
• a first bit line extending in a first direction, being coupled to at least the first memory cell, and being on at least a first metal layer or a second metal layer above a front-side of a substrate;
• a first bit line bar extending in the first direction, being coupled to at least the first memory cell, and being on at least the first metal layer or the second metal layer;
• a second bit line extending in the first direction, being coupled to at least the second memory cell, and being on at least a third metal layer or a fourth metal layer below a back-side of the substrate opposite from the front-side of the substrate;
• and
• a second bit line bar extending in the first direction, being coupled to at least the second memory cell, and being on at least the third metal layer or the fourth metal layer,
• wherein the first bit line and the first bit line bar overlap the first bank of memory cells and the second bank of memory cells, and
• the second bit line and the second bit line bar extend within the second bank of memory cells.

A method of fabricating a memory cell array, the method comprising:

• fabricating a first set of transistors and a second set of transistors in a front-side of a substrate, the first set of transistors being stacked above the second set of transistors, the first set of transistors including a first pass-gate transistor and a second pass-gate transistor of a first type;
• fabricating a third set of transistors and a fourth set of transistors in the front-side of the substrate, the third set of transistors being stacked above the fourth set of transistors, the fourth set of transistors including a third pass-gate transistor and a fourth pass-gate transistor of a second type different from the first type;
• fabricating a first set of vias on the front-side of the substrate, the first set of vias being electrically coupled to at least the first set of transistors or the second set of transistors;
• depositing a first conductive material on the front-side of the substrate on a first metal level thereby forming a first set of conductors, the first set of conductors being electrically coupled to at least the first set of transistors or the second set of transistors by the first set of vias, the first set of transistors or the second set of transistors being configured to receive a first bit line signal from at least a first conductor of the first set of conductors from the front-side, and a first bit line bar signal from at least a second conductor of the first set of conductors from the front-side;
• performing thinning on a back-side of the substrate opposite from the front-side;
• fabricating a second set of vias on the back-side of the thinned substrate, the second set of vias being electrically coupled to at least the third set of transistors or the fourth set of transistors;
• and
• depositing a second conductive material on the front-side of the substrate on a second metal level thereby forming a second set of conductors, the second set of conductors being electrically coupled to at least the third set of transistors or the fourth set of transistors by the second set of vias, the third set of transistors or the fourth set of transistors being configured to receive a second bit line signal from at least a first conductor of the second set of conductors from the back-side, and a second bit line bar signal from at least a second conductor of the second set of conductors from the back-side.