Memory management using a register
AssigneeNVIDIA Corporation
InventorsJack H. Choquette, Stephen Anthony Bernard Jones, Maciej Piotr Tyrlik, Harold Carter Edwards, Manan Patel
Life of this patent
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AssigneeNVIDIA Corporation
InventorsJack H. Choquette, Stephen Anthony Bernard Jones, Maciej Piotr Tyrlik, Harold Carter Edwards, Manan Patel
Estimating the term…
A first request to allocate one or more memory blocks of a first plurality of memory blocks associated with a first memory is received by a processing device. A consecutive set of a first portion of bits of a first register with a first logical state is identified. The first logical state indicates that corresponding memory blocks of the one or more memory blocks are free. A first operation to adjust the consecutive set of the first portion of bits of the first register to a second logical state is performed. An allocation address comprising an index of the consecutive set of the first portion of bits of the first register is sent to the first request. The allocation address is useable to access the corresponding memory blocks.
A system comprising:
A method comprising:
A parallel processing unit (PPU) comprising:
Dependencies are inferred from the claim text.