Flexible memory system
AssigneeAdvanced Micro Devices, Inc.
InventorsVidyashankar Viswanathan, Richard E. George, Michael Y. Chow
Life of this patent
Estimating the term…
Abstract
A technique for operating a memory system is disclosed. The technique includes performing a first request, by a first memory client, to access data at a first memory address, wherein the first memory address refers to data in a first memory section that is coupled to the first memory client via a direct memory connection; servicing the first request via the direct memory connection; performing a second request, by the first client, to access data at a second memory address, wherein the second memory address refers to data in a second memory section that is coupled to the first client via a cross connection; and servicing the second request via the cross connection.
Claims20
A method comprising:
- requesting access to a first memory address for a first memory client of a plurality of memory clients, the first memory address being mapped to a first memory on a first chip coupled to the first memory client via a first direct connection through an interconnect die;
- servicing the request to the first memory address via the first direct connection;
- requesting access to a second memory address for the first memory client, the second memory address being mapped to a second memory on a second chip coupled to the first memory client via a cross connection between the first direct connection and a second direct connection through the interconnect die;
- and
- servicing the request to the second memory address via the cross connection.
A system comprising:
- a first chip including a first memory;
- a second chip including a second memory;
- and
- a first memory client coupled to the first memory via a direct connection through an interconnect die and to the second memory via a cross connection between the direct connection and a second direct connection through the interconnect die, the first memory client configured to:
- request access to a first memory address mapped to the first memory, and
- request access to a second memory address mapped to the second memory;
- wherein the first memory is configured to service the access to the first memory address via the direct connection;
- and
- wherein the second memory is configured to service the access to the second memory address via the cross connection.
A system comprising:
- a first chip including a first memory;
- a second chip including a second memory;
- a first memory client;
- a second memory client;
- and
- an interconnect die that includes a first direct connection between the first chip and the first memory client, a second direct connection between the second chip and the second memory client, and a first cross connection between the first direct connection and the second direct connection,
- wherein the first memory client is coupled to the first memory via the first direct connection and to the second memory via the first cross connection;
- and
- wherein the second memory client is coupled to the first memory via a second cross connection and to the second memory via the second direct connection,
- wherein the first memory client is configured to:
- request access to a first memory address mapped to the first memory, and
- request access to a second memory address mapped to the second memory;
- wherein the first memory is configured to service the access to the first memory address via the first direct connection;
- and
- wherein the second memory is configured to service the access to the second memory address via the first cross connection.
Dependencies are inferred from the claim text.