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US 12,596,395 B2Granted
Handshaking mechanism for clock network control
AssigneeATI Technologies ULC
InventorErwin Pang
Life of this patent
Estimating the term…
Abstract
A method for clock distribution network control includes determining, at a first clock node of a plurality of clock nodes within a clock distribution network, a downstream clock request status. A clock request signal is transmitted by the first clock node to an upstream parent node based on the downstream clock request status. A clock buffer of the first clock node is toggled based at least in part on the clock request signal to the parent node. If the first clock node receives an asserted clock request signal from one or more downstream child nodes and clock acknowledgment signal from the parent node, a clock enable signal is asserted to the clock buffer to output a clock signal to the one or more downstream child nodes.
Claims18
A method, comprising:
- transmitting, by an upstream clock interface of clock control circuitry of a first clock node of a plurality of clock nodes within a clock distribution network for a single clock source and based at least in part on a downstream clock request status received at one or more downstream clock interfaces of the clock control circuitry, a clock request signal to a parent node upstream of the first clock node;
- enabling a clock buffer of the clock control circuitry to turn on clock signal distribution based at least in part on the one or more downstream clock interfaces receiving an asserted clock request signal from one or more child nodes downstream of the first clock node;
- toggling, based at least in part on the clock request signal to the parent node, the clock buffer of the first clock node, wherein the clock buffer is configured to distribute a clock signal to the one or more child nodes downstream of the first clock node;
- and
- turning off the clock buffer of the first clock node based at least in part on not receiving an asserted clock request signal from the one or more child nodes downstream of the first clock node while keeping on a clock buffer of a second clock node of the plurality of clock nodes within the clock distribution network for the single clock source based at least in part on the second clock node receiving an asserted clock request signal from one or more child nodes downstream of the second clock node.
2 more elements
A system, comprising:
- a single clock source;
- and
- a clock distribution network for the single clock source, wherein the clock distribution network includes:
- a plurality of clock nodes, each clock node comprising clock control circuitry comprising an upstream clock interface, one or more downstream clock interfaces, and a clock buffer;
- a first clock node of the plurality of clock nodes, wherein the first clock node is to enable the clock buffer of the first clock node to turn on clock signal distribution to a child node downstream of the first clock node based at least in part on a downstream clock request status received from the child node at the one or more downstream clock interfaces of the clock control circuitry of the first clock node, and wherein the first clock node is to turn off the clock buffer based at least in part on not receiving an asserted clock request signal from one or more child nodes downstream of the first clock node;
- a second clock node of the plurality of clock nodes, comprising a clock buffer that is kept on based at least in part on the second clock node receiving at the one or more downstream clock interfaces of the clock control circuitry of the second clock node an asserted clock request signal from one or more child nodes downstream of the second clock node, wherein the clock control circuitry of the second clock node is to initiate a clock request signal via the upstream clock interface of the clock control circuitry of the second clock node;
- and
- a parent clock node upstream of the second clock node, wherein the parent node is configured to receive the clock request signal from the second clock node based at least in part on the downstream clock request status.
5 more elements
An integrated circuit device, comprising:
- a single clock source that drives a clock distribution network,
- wherein the clock distribution network includes:
- a plurality of clock nodes, each clock node comprising clock control circuitry comprising an upstream clock interface, one or more downstream clock interfaces;
- a first clock node of the plurality of clock nodes, wherein the first clock node is configured to transmit a clock request signal via the upstream clock interface of the clock control circuitry of the first clock node based at least in part on a downstream clock request status received at the one or more downstream clock interfaces of the clock control circuitry of the first clock node from a child node downstream of the first clock node and toggle a first clock buffer of the first clock node to distribute a clock signal to one or more child nodes downstream of the first clock node, wherein the first clock node is to turn off the first clock buffer based at least in part on not receiving an asserted clock request signal from one or more child nodes downstream of the first clock node;
- and
- a second clock node of the plurality of clock nodes, comprising a second clock buffer that is kept on based at least in part on the second clock node receiving an asserted clock request signal at the one or more downstream clock interfaces of the clock control circuitry of the second clock node from one or more child nodes downstream of the second clock node.
3 more elements
Dependencies are inferred from the claim text.