Flip chip package for semiconductor devices

A multilayer package substrate, comprising:

• a die mount area on a die side surface and power pads and ground pads on an opposing board side surface, the multilayer package substrate further comprising post connect locations on the die side surface configured for receiving power post connects and for receiving ground post connects for mounting a flip chip mounted semiconductor device, power post connect locations and ground post connect locations intermixed in the die mount area,
• wherein the multilayer package substrate further comprises:
• a first conductive trace layer on the die side surface in a first layer of dielectric including the post connect locations configured to receive the ground post connects and the power post connects, the ground post connect locations electrically isolated from the power post connect locations by the first layer of dielectric;
• a first vertical connection layer underlying the first conductive trace layer and having conductor patterns in a second layer of dielectric, portions of the first vertical connection layer connected to the power post connect locations on the first conductive trace layer to form power connections, and portions of the first vertical connection layer connected to the ground post connect locations on the first conductive trace layer to form ground connections;
• a second conductive trace layer underlying the first vertical connection layer, the second conductive trace layer having conductors in a third layer of dielectric, the second conductive trace layer comprising a ground plane connected to the ground connections of the first vertical connection layer for carrying a ground potential, and the second conductive trace layer further comprising a power plane connected to the power connections of the first vertical connection layer for carrying a power potential;
• and
• a second vertical connection layer in a fourth layer of dielectric comprising one or more of the ground pads coupled to the ground plane of the second conductive trace layer, and the second vertical connection layer comprising one or more of the power pads coupled to the power plane of the second conductive trace layer.

A method of manufacturing a semiconductor package, comprising:

• positioning a semiconductor device having post connects extending from bond pads on a device side surface of the semiconductor device over a die mount area on a multilayer package substrate, the multilayer package substrate comprising a die side surface with the die mount area and power pads and ground pads on an opposing board side surface, the multilayer package substrate further comprising post connect locations on the die side surface configured for receiving power post connects and for receiving ground post connects for the semiconductor device, power post connect locations and ground post connect locations positioned in the die mount area, the power post connect locations and the ground post connect locations intermixed in the die mount area;
• forming solder joints between the post connects extending from the semiconductor device and the post connect locations of the multilayer package substrate to electrically couple the semiconductor device to the multilayer package substrate;
• and
• covering the semiconductor device and the die side surface of the multilayer package substrate in mold compound.