Semiconductor package

A semiconductor package, comprising:

• a first substrate;
• a semiconductor chip provided on the first substrate;
• conductive structures provided on the first substrate and laterally spaced apart from the semiconductor chip;
• and
• a second substrate provided on the semiconductor chip and the conductive structures,
• wherein the conductive structures comprise a first conductive structure, a second conductive structure, and a third conductive structure, which are adjacent to each other,
• wherein the third conductive structure is provided between, and electrically isolated from, the first and second conductive structures,
• wherein the first conductive structure, the third conductive structure and the second conductive structure are spaced apart from the semiconductor chip in sequence,
• wherein the second substrate comprises:
• a first redistribution pattern electrically connected to the first conductive structure, and vertically overlaps the semiconductor chip;
• a second redistribution pattern electrically connected to the second conductive structure;
• and
• a third redistribution pattern electrically connected to the third conductive structure,
• wherein an area of a top surface of the first redistribution pattern is larger than an area of a top surface of the third redistribution pattern,
• wherein an area of a top surface of the second redistribution pattern is larger than the area of the top surface of the third redistribution pattern,
• wherein the first conductive structure and the second conductive structure are configured to provide a ground or a power voltage, and
• wherein at least one of the first conductive structure and the second conductive structure is configured to provide the power voltage.

A semiconductor package, comprising:

• a first substrate comprising a first insulating layer, under-bump patterns, under-bump seed patterns, a first ground/power conductive pattern, a second ground/power conductive pattern, and a signal conductive pattern;
• a semiconductor chip provided on a top surface of the first substrate;
• conductive structures provided on the top surface of the first substrate, and laterally spaced apart from both the semiconductor chip and from each other;
• a mold layer provided on the top surface of the first substrate, side surfaces of the semiconductor chip and side surfaces of the conductive structures;
• and
• a second substrate provided on the mold layer and the conductive structures, and electrically connected to the conductive structures,
• wherein the conductive structures comprise:
• a first conductive structure coupled to the first ground/power conductive pattern;
• a second conductive structure coupled to the second ground/power conductive pattern;
• a third conductive structure coupled to the signal conductive pattern;
• and
• a fourth conductive structure coupled to the first ground/power conductive pattern,
• wherein the third conductive structure is provided between the first and second conductive structures, and
• wherein the under-bump seed patterns are provided on side surfaces of the under-bump patterns, and have lower surfaces that are spaced apart from bottom surfaces of the under-bump patterns and are between an upper surface of the first insulating layer and a lower surface of the first insulating layer.